869 lines
33 KiB
C++
869 lines
33 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <utility>
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#include "shader_recompiler/backend/glasm/emit_context.h"
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#include "shader_recompiler/backend/glasm/emit_glasm_instructions.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/ir/value.h"
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namespace Shader::Backend::GLASM {
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namespace {
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struct ScopedRegister {
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ScopedRegister() = default;
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ScopedRegister(RegAlloc& reg_alloc_) : reg_alloc{®_alloc_}, reg{reg_alloc->AllocReg()} {}
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~ScopedRegister() {
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if (reg_alloc) {
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reg_alloc->FreeReg(reg);
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}
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}
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ScopedRegister& operator=(ScopedRegister&& rhs) noexcept {
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if (reg_alloc) {
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reg_alloc->FreeReg(reg);
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}
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reg_alloc = std::exchange(rhs.reg_alloc, nullptr);
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reg = rhs.reg;
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return *this;
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}
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ScopedRegister(ScopedRegister&& rhs) noexcept
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: reg_alloc{std::exchange(rhs.reg_alloc, nullptr)}, reg{rhs.reg} {}
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ScopedRegister& operator=(const ScopedRegister&) = delete;
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ScopedRegister(const ScopedRegister&) = delete;
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RegAlloc* reg_alloc{};
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Register reg;
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};
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std::string Texture(EmitContext& ctx, IR::TextureInstInfo info,
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[[maybe_unused]] const IR::Value& index) {
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// FIXME: indexed reads
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if (info.type == TextureType::Buffer) {
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return fmt::format("texture[{}]", ctx.texture_buffer_bindings.at(info.descriptor_index));
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} else {
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return fmt::format("texture[{}]", ctx.texture_bindings.at(info.descriptor_index));
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}
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}
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std::string Image(EmitContext& ctx, IR::TextureInstInfo info,
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[[maybe_unused]] const IR::Value& index) {
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// FIXME: indexed reads
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if (info.type == TextureType::Buffer) {
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return fmt::format("image[{}]", ctx.image_buffer_bindings.at(info.descriptor_index));
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} else {
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return fmt::format("image[{}]", ctx.image_bindings.at(info.descriptor_index));
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}
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}
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std::string_view TextureType(IR::TextureInstInfo info) {
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if (info.is_depth) {
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switch (info.type) {
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case TextureType::Color1D:
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return "SHADOW1D";
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case TextureType::ColorArray1D:
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return "SHADOWARRAY1D";
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case TextureType::Color2D:
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return "SHADOW2D";
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case TextureType::ColorArray2D:
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return "SHADOWARRAY2D";
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case TextureType::Color3D:
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return "SHADOW3D";
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case TextureType::ColorCube:
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return "SHADOWCUBE";
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case TextureType::ColorArrayCube:
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return "SHADOWARRAYCUBE";
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case TextureType::Buffer:
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return "SHADOWBUFFER";
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}
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} else {
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switch (info.type) {
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case TextureType::Color1D:
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return "1D";
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case TextureType::ColorArray1D:
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return "ARRAY1D";
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case TextureType::Color2D:
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return "2D";
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case TextureType::ColorArray2D:
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return "ARRAY2D";
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case TextureType::Color3D:
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return "3D";
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case TextureType::ColorCube:
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return "CUBE";
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case TextureType::ColorArrayCube:
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return "ARRAYCUBE";
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case TextureType::Buffer:
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return "BUFFER";
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}
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}
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throw InvalidArgument("Invalid texture type {}", info.type.Value());
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}
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std::string Offset(EmitContext& ctx, const IR::Value& offset) {
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if (offset.IsEmpty()) {
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return "";
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}
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return fmt::format(",offset({})", Register{ctx.reg_alloc.Consume(offset)});
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}
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std::pair<ScopedRegister, ScopedRegister> AllocOffsetsRegs(EmitContext& ctx,
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const IR::Value& offset2) {
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if (offset2.IsEmpty()) {
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return {};
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} else {
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return {ctx.reg_alloc, ctx.reg_alloc};
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}
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}
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void SwizzleOffsets(EmitContext& ctx, Register off_x, Register off_y, const IR::Value& offset1,
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const IR::Value& offset2) {
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const Register offsets_a{ctx.reg_alloc.Consume(offset1)};
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const Register offsets_b{ctx.reg_alloc.Consume(offset2)};
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// Input swizzle: [XYXY] [XYXY]
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// Output swizzle: [XXXX] [YYYY]
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ctx.Add("MOV {}.x,{}.x;"
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"MOV {}.y,{}.z;"
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"MOV {}.z,{}.x;"
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"MOV {}.w,{}.z;"
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"MOV {}.x,{}.y;"
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"MOV {}.y,{}.w;"
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"MOV {}.z,{}.y;"
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"MOV {}.w,{}.w;",
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off_x, offsets_a, off_x, offsets_a, off_x, offsets_b, off_x, offsets_b, off_y,
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offsets_a, off_y, offsets_a, off_y, offsets_b, off_y, offsets_b);
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}
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std::string GradOffset(const IR::Value& offset) {
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if (offset.IsImmediate()) {
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LOG_WARNING(Shader_GLASM, "Gradient offset is a scalar immediate");
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return "";
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}
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IR::Inst* const vector{offset.InstRecursive()};
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if (!vector->AreAllArgsImmediates()) {
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LOG_WARNING(Shader_GLASM, "Gradient offset vector is not immediate");
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return "";
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}
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switch (vector->NumArgs()) {
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case 1:
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return fmt::format(",({})", static_cast<s32>(vector->Arg(0).U32()));
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case 2:
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return fmt::format(",({},{})", static_cast<s32>(vector->Arg(0).U32()),
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static_cast<s32>(vector->Arg(1).U32()));
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default:
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throw LogicError("Invalid number of gradient offsets {}", vector->NumArgs());
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}
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}
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std::pair<std::string, ScopedRegister> Coord(EmitContext& ctx, const IR::Value& coord) {
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if (coord.IsImmediate()) {
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ScopedRegister scoped_reg(ctx.reg_alloc);
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ctx.Add("MOV.U {}.x,{};", scoped_reg.reg, ScalarU32{ctx.reg_alloc.Consume(coord)});
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return {fmt::to_string(scoped_reg.reg), std::move(scoped_reg)};
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}
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std::string coord_vec{fmt::to_string(Register{ctx.reg_alloc.Consume(coord)})};
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if (coord.InstRecursive()->HasUses()) {
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// Move non-dead coords to a separate register, although this should never happen because
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// vectors are only assembled for immediate texture instructions
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ctx.Add("MOV.F RC,{};", coord_vec);
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coord_vec = "RC";
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}
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return {std::move(coord_vec), ScopedRegister{}};
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}
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void StoreSparse(EmitContext& ctx, IR::Inst* sparse_inst) {
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if (!sparse_inst) {
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return;
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}
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const Register sparse_ret{ctx.reg_alloc.Define(*sparse_inst)};
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ctx.Add("MOV.S {},-1;"
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"MOV.S {}(NONRESIDENT),0;",
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sparse_ret, sparse_ret);
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}
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std::string_view FormatStorage(ImageFormat format) {
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switch (format) {
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case ImageFormat::Typeless:
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return "U";
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case ImageFormat::R8_UINT:
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return "U8";
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case ImageFormat::R8_SINT:
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return "S8";
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case ImageFormat::R16_UINT:
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return "U16";
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case ImageFormat::R16_SINT:
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return "S16";
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case ImageFormat::R32_UINT:
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return "U32";
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case ImageFormat::R32G32_UINT:
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return "U32X2";
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case ImageFormat::R32G32B32A32_UINT:
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return "U32X4";
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}
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throw InvalidArgument("Invalid image format {}", format);
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}
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template <typename T>
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void ImageAtomic(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord, T value,
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std::string_view op) {
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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const std::string_view type{TextureType(info)};
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const std::string image{Image(ctx, info, index)};
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const Register ret{ctx.reg_alloc.Define(inst)};
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ctx.Add("ATOMIM.{} {},{},{},{},{};", op, ret, value, coord, image, type);
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}
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IR::Inst* PrepareSparse(IR::Inst& inst) {
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const auto sparse_inst{inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp)};
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if (sparse_inst) {
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sparse_inst->Invalidate();
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}
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return sparse_inst;
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}
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} // Anonymous namespace
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void EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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const IR::Value& coord, Register bias_lc, const IR::Value& offset) {
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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const auto sparse_inst{PrepareSparse(inst)};
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const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
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const std::string_view lod_clamp_mod{info.has_lod_clamp ? ".LODCLAMP" : ""};
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const std::string_view type{TextureType(info)};
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const std::string texture{Texture(ctx, info, index)};
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const std::string offset_vec{Offset(ctx, offset)};
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const auto [coord_vec, coord_alloc]{Coord(ctx, coord)};
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (info.has_bias) {
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if (info.type == TextureType::ColorArrayCube) {
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ctx.Add("TXB.F{}{} {},{},{},{},ARRAYCUBE{};", lod_clamp_mod, sparse_mod, ret, coord_vec,
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bias_lc, texture, offset_vec);
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} else {
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if (info.has_lod_clamp) {
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ctx.Add("MOV.F {}.w,{}.x;"
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"TXB.F.LODCLAMP{} {},{},{}.y,{},{}{};",
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coord_vec, bias_lc, sparse_mod, ret, coord_vec, bias_lc, texture, type,
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offset_vec);
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} else {
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ctx.Add("MOV.F {}.w,{}.x;"
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"TXB.F{} {},{},{},{}{};",
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coord_vec, bias_lc, sparse_mod, ret, coord_vec, texture, type, offset_vec);
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}
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}
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} else {
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if (info.has_lod_clamp && info.type == TextureType::ColorArrayCube) {
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ctx.Add("TEX.F.LODCLAMP{} {},{},{},{},ARRAYCUBE{};", sparse_mod, ret, coord_vec,
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bias_lc, texture, offset_vec);
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} else {
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ctx.Add("TEX.F{}{} {},{},{},{}{};", lod_clamp_mod, sparse_mod, ret, coord_vec, texture,
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type, offset_vec);
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}
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}
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StoreSparse(ctx, sparse_inst);
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}
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void EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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const IR::Value& coord, ScalarF32 lod, const IR::Value& offset) {
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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const auto sparse_inst{PrepareSparse(inst)};
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const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
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const std::string_view type{TextureType(info)};
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const std::string texture{Texture(ctx, info, index)};
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const std::string offset_vec{Offset(ctx, offset)};
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const auto [coord_vec, coord_alloc]{Coord(ctx, coord)};
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (info.type == TextureType::ColorArrayCube) {
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ctx.Add("TXL.F{} {},{},{},{},ARRAYCUBE{};", sparse_mod, ret, coord_vec, lod, texture,
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offset_vec);
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} else {
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ctx.Add("MOV.F {}.w,{};"
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"TXL.F{} {},{},{},{}{};",
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coord_vec, lod, sparse_mod, ret, coord_vec, texture, type, offset_vec);
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}
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StoreSparse(ctx, sparse_inst);
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}
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void EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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const IR::Value& coord, const IR::Value& dref,
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const IR::Value& bias_lc, const IR::Value& offset) {
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// Allocate early to avoid aliases
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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ScopedRegister staging;
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if (info.type == TextureType::ColorArrayCube) {
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staging = ScopedRegister{ctx.reg_alloc};
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}
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const ScalarF32 dref_val{ctx.reg_alloc.Consume(dref)};
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const Register bias_lc_vec{ctx.reg_alloc.Consume(bias_lc)};
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const auto sparse_inst{PrepareSparse(inst)};
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const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
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const std::string_view type{TextureType(info)};
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const std::string texture{Texture(ctx, info, index)};
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const std::string offset_vec{Offset(ctx, offset)};
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const auto [coord_vec, coord_alloc]{Coord(ctx, coord)};
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const Register ret{ctx.reg_alloc.Define(inst)};
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if (info.has_bias) {
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if (info.has_lod_clamp) {
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switch (info.type) {
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case TextureType::Color1D:
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case TextureType::ColorArray1D:
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case TextureType::Color2D:
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ctx.Add("MOV.F {}.z,{};"
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"MOV.F {}.w,{}.x;"
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"TXB.F.LODCLAMP{} {},{},{}.y,{},{}{};",
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coord_vec, dref_val, coord_vec, bias_lc_vec, sparse_mod, ret, coord_vec,
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bias_lc_vec, texture, type, offset_vec);
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break;
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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ctx.Add("MOV.F {}.w,{};"
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"TXB.F.LODCLAMP{} {},{},{},{},{}{};",
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coord_vec, dref_val, sparse_mod, ret, coord_vec, bias_lc_vec, texture, type,
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offset_vec);
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break;
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default:
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throw NotImplementedException("Invalid type {} with bias and lod clamp",
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info.type.Value());
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}
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} else {
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switch (info.type) {
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case TextureType::Color1D:
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case TextureType::ColorArray1D:
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case TextureType::Color2D:
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ctx.Add("MOV.F {}.z,{};"
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"MOV.F {}.w,{}.x;"
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"TXB.F{} {},{},{},{}{};",
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coord_vec, dref_val, coord_vec, bias_lc_vec, sparse_mod, ret, coord_vec,
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texture, type, offset_vec);
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break;
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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ctx.Add("MOV.F {}.w,{};"
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"TXB.F{} {},{},{},{},{}{};",
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coord_vec, dref_val, sparse_mod, ret, coord_vec, bias_lc_vec, texture, type,
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offset_vec);
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break;
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case TextureType::ColorArrayCube:
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ctx.Add("MOV.F {}.x,{};"
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"MOV.F {}.y,{}.x;"
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"TXB.F{} {},{},{},{},{}{};",
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staging.reg, dref_val, staging.reg, bias_lc_vec, sparse_mod, ret, coord_vec,
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staging.reg, texture, type, offset_vec);
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break;
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default:
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throw NotImplementedException("Invalid type {}", info.type.Value());
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}
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}
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} else {
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if (info.has_lod_clamp) {
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if (info.type != TextureType::ColorArrayCube) {
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const bool w_swizzle{info.type == TextureType::ColorArray2D ||
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info.type == TextureType::ColorCube};
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const char dref_swizzle{w_swizzle ? 'w' : 'z'};
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ctx.Add("MOV.F {}.{},{};"
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"TEX.F.LODCLAMP{} {},{},{},{},{}{};",
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coord_vec, dref_swizzle, dref_val, sparse_mod, ret, coord_vec, bias_lc_vec,
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texture, type, offset_vec);
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} else {
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ctx.Add("MOV.F {}.x,{};"
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"MOV.F {}.y,{};"
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"TEX.F.LODCLAMP{} {},{},{},{},{}{};",
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staging.reg, dref_val, staging.reg, bias_lc_vec, sparse_mod, ret, coord_vec,
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staging.reg, texture, type, offset_vec);
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}
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} else {
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if (info.type != TextureType::ColorArrayCube) {
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const bool w_swizzle{info.type == TextureType::ColorArray2D ||
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info.type == TextureType::ColorCube};
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const char dref_swizzle{w_swizzle ? 'w' : 'z'};
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ctx.Add("MOV.F {}.{},{};"
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"TEX.F{} {},{},{},{}{};",
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coord_vec, dref_swizzle, dref_val, sparse_mod, ret, coord_vec, texture,
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type, offset_vec);
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} else {
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ctx.Add("TEX.F{} {},{},{},{},{}{};", sparse_mod, ret, coord_vec, dref_val, texture,
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type, offset_vec);
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}
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}
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}
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StoreSparse(ctx, sparse_inst);
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}
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void EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
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const IR::Value& coord, const IR::Value& dref,
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const IR::Value& lod, const IR::Value& offset) {
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// Allocate early to avoid aliases
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const auto info{inst.Flags<IR::TextureInstInfo>()};
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ScopedRegister staging;
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if (info.type == TextureType::ColorArrayCube) {
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staging = ScopedRegister{ctx.reg_alloc};
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}
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const ScalarF32 dref_val{ctx.reg_alloc.Consume(dref)};
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const ScalarF32 lod_val{ctx.reg_alloc.Consume(lod)};
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const auto sparse_inst{PrepareSparse(inst)};
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const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
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const std::string_view type{TextureType(info)};
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const std::string texture{Texture(ctx, info, index)};
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const std::string offset_vec{Offset(ctx, offset)};
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const auto [coord_vec, coord_alloc]{Coord(ctx, coord)};
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const Register ret{ctx.reg_alloc.Define(inst)};
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switch (info.type) {
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case TextureType::Color1D:
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case TextureType::ColorArray1D:
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case TextureType::Color2D:
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ctx.Add("MOV.F {}.z,{};"
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"MOV.F {}.w,{};"
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"TXL.F{} {},{},{},{}{};",
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coord_vec, dref_val, coord_vec, lod_val, sparse_mod, ret, coord_vec, texture, type,
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offset_vec);
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break;
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case TextureType::ColorArray2D:
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case TextureType::ColorCube:
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ctx.Add("MOV.F {}.w,{};"
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"TXL.F{} {},{},{},{},{}{};",
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coord_vec, dref_val, sparse_mod, ret, coord_vec, lod_val, texture, type,
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offset_vec);
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break;
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case TextureType::ColorArrayCube:
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ctx.Add("MOV.F {}.x,{};"
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"MOV.F {}.y,{};"
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"TXL.F{} {},{},{},{},{}{};",
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staging.reg, dref_val, staging.reg, lod_val, sparse_mod, ret, coord_vec,
|
|
staging.reg, texture, type, offset_vec);
|
|
break;
|
|
default:
|
|
throw NotImplementedException("Invalid type {}", info.type.Value());
|
|
}
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageGather(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
const IR::Value& coord, const IR::Value& offset, const IR::Value& offset2) {
|
|
// Allocate offsets early so they don't overwrite any consumed register
|
|
const auto [off_x, off_y]{AllocOffsetsRegs(ctx, offset2)};
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const char comp{"xyzw"[info.gather_component]};
|
|
const auto sparse_inst{PrepareSparse(inst)};
|
|
const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const Register coord_vec{ctx.reg_alloc.Consume(coord)};
|
|
const Register ret{ctx.reg_alloc.Define(inst)};
|
|
if (offset2.IsEmpty()) {
|
|
const std::string offset_vec{Offset(ctx, offset)};
|
|
ctx.Add("TXG.F{} {},{},{}.{},{}{};", sparse_mod, ret, coord_vec, texture, comp, type,
|
|
offset_vec);
|
|
} else {
|
|
SwizzleOffsets(ctx, off_x.reg, off_y.reg, offset, offset2);
|
|
ctx.Add("TXGO.F{} {},{},{},{},{}.{},{};", sparse_mod, ret, coord_vec, off_x.reg, off_y.reg,
|
|
texture, comp, type);
|
|
}
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageGatherDref(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
const IR::Value& coord, const IR::Value& offset, const IR::Value& offset2,
|
|
const IR::Value& dref) {
|
|
// FIXME: This instruction is not working as expected
|
|
|
|
// Allocate offsets early so they don't overwrite any consumed register
|
|
const auto [off_x, off_y]{AllocOffsetsRegs(ctx, offset2)};
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const auto sparse_inst{PrepareSparse(inst)};
|
|
const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const Register coord_vec{ctx.reg_alloc.Consume(coord)};
|
|
const ScalarF32 dref_value{ctx.reg_alloc.Consume(dref)};
|
|
const Register ret{ctx.reg_alloc.Define(inst)};
|
|
std::string args;
|
|
switch (info.type) {
|
|
case TextureType::Color2D:
|
|
ctx.Add("MOV.F {}.z,{};", coord_vec, dref_value);
|
|
args = fmt::to_string(coord_vec);
|
|
break;
|
|
case TextureType::ColorArray2D:
|
|
case TextureType::ColorCube:
|
|
ctx.Add("MOV.F {}.w,{};", coord_vec, dref_value);
|
|
args = fmt::to_string(coord_vec);
|
|
break;
|
|
case TextureType::ColorArrayCube:
|
|
args = fmt::format("{},{}", coord_vec, dref_value);
|
|
break;
|
|
default:
|
|
throw NotImplementedException("Invalid type {}", info.type.Value());
|
|
}
|
|
if (offset2.IsEmpty()) {
|
|
const std::string offset_vec{Offset(ctx, offset)};
|
|
ctx.Add("TXG.F{} {},{},{},{}{};", sparse_mod, ret, args, texture, type, offset_vec);
|
|
} else {
|
|
SwizzleOffsets(ctx, off_x.reg, off_y.reg, offset, offset2);
|
|
ctx.Add("TXGO.F{} {},{},{},{},{},{};", sparse_mod, ret, args, off_x.reg, off_y.reg, texture,
|
|
type);
|
|
}
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageFetch(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
const IR::Value& coord, const IR::Value& offset, ScalarS32 lod, ScalarS32 ms) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const auto sparse_inst{PrepareSparse(inst)};
|
|
const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const std::string offset_vec{Offset(ctx, offset)};
|
|
const auto [coord_vec, coord_alloc]{Coord(ctx, coord)};
|
|
const Register ret{ctx.reg_alloc.Define(inst)};
|
|
if (info.type == TextureType::Buffer) {
|
|
ctx.Add("TXF.F{} {},{},{},{}{};", sparse_mod, ret, coord_vec, texture, type, offset_vec);
|
|
} else if (ms.type != Type::Void) {
|
|
ctx.Add("MOV.S {}.w,{};"
|
|
"TXFMS.F{} {},{},{},{}{};",
|
|
coord_vec, ms, sparse_mod, ret, coord_vec, texture, type, offset_vec);
|
|
} else {
|
|
ctx.Add("MOV.S {}.w,{};"
|
|
"TXF.F{} {},{},{},{}{};",
|
|
coord_vec, lod, sparse_mod, ret, coord_vec, texture, type, offset_vec);
|
|
}
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageQueryDimensions(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
ScalarS32 lod) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const std::string_view type{TextureType(info)};
|
|
ctx.Add("TXQ {},{},{},{};", inst, lod, texture, type);
|
|
}
|
|
|
|
void EmitImageQueryLod(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const std::string_view type{TextureType(info)};
|
|
ctx.Add("LOD.F {},{},{},{};", inst, coord, texture, type);
|
|
}
|
|
|
|
void EmitImageGradient(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
const IR::Value& coord, const IR::Value& derivatives,
|
|
const IR::Value& offset, const IR::Value& lod_clamp) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
ScopedRegister dpdx, dpdy;
|
|
const bool multi_component{info.num_derivates > 1 || info.has_lod_clamp};
|
|
if (multi_component) {
|
|
// Allocate this early to avoid aliasing other registers
|
|
dpdx = ScopedRegister{ctx.reg_alloc};
|
|
dpdy = ScopedRegister{ctx.reg_alloc};
|
|
}
|
|
const auto sparse_inst{PrepareSparse(inst)};
|
|
const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string texture{Texture(ctx, info, index)};
|
|
const std::string offset_vec{GradOffset(offset)};
|
|
const Register coord_vec{ctx.reg_alloc.Consume(coord)};
|
|
const Register derivatives_vec{ctx.reg_alloc.Consume(derivatives)};
|
|
const Register ret{ctx.reg_alloc.Define(inst)};
|
|
if (multi_component) {
|
|
ctx.Add("MOV.F {}.x,{}.x;"
|
|
"MOV.F {}.y,{}.z;"
|
|
"MOV.F {}.x,{}.y;"
|
|
"MOV.F {}.y,{}.w;",
|
|
dpdx.reg, derivatives_vec, dpdx.reg, derivatives_vec, dpdy.reg, derivatives_vec,
|
|
dpdy.reg, derivatives_vec);
|
|
if (info.has_lod_clamp) {
|
|
const ScalarF32 lod_clamp_value{ctx.reg_alloc.Consume(lod_clamp)};
|
|
ctx.Add("MOV.F {}.w,{};"
|
|
"TXD.F.LODCLAMP{} {},{},{},{},{},{}{};",
|
|
dpdy.reg, lod_clamp_value, sparse_mod, ret, coord_vec, dpdx.reg, dpdy.reg,
|
|
texture, type, offset_vec);
|
|
} else {
|
|
ctx.Add("TXD.F{} {},{},{},{},{},{}{};", sparse_mod, ret, coord_vec, dpdx.reg, dpdy.reg,
|
|
texture, type, offset_vec);
|
|
}
|
|
} else {
|
|
ctx.Add("TXD.F{} {},{},{}.x,{}.y,{},{}{};", sparse_mod, ret, coord_vec, derivatives_vec,
|
|
derivatives_vec, texture, type, offset_vec);
|
|
}
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageRead(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const auto sparse_inst{PrepareSparse(inst)};
|
|
const std::string_view format{FormatStorage(info.image_format)};
|
|
const std::string_view sparse_mod{sparse_inst ? ".SPARSE" : ""};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string image{Image(ctx, info, index)};
|
|
const Register ret{ctx.reg_alloc.Define(inst)};
|
|
ctx.Add("LOADIM.{}{} {},{},{},{};", format, sparse_mod, ret, coord, image, type);
|
|
StoreSparse(ctx, sparse_inst);
|
|
}
|
|
|
|
void EmitImageWrite(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
Register color) {
|
|
const auto info{inst.Flags<IR::TextureInstInfo>()};
|
|
const std::string_view format{FormatStorage(info.image_format)};
|
|
const std::string_view type{TextureType(info)};
|
|
const std::string image{Image(ctx, info, index)};
|
|
ctx.Add("STOREIM.{} {},{},{},{};", format, image, color, coord, type);
|
|
}
|
|
|
|
void EmitIsTextureScaled(EmitContext& ctx, IR::Inst& inst, const IR::Value& index) {
|
|
if (!index.IsImmediate()) {
|
|
throw NotImplementedException("Non-constant texture rescaling");
|
|
}
|
|
ctx.Add("AND.U RC.x,scaling[0].x,{};"
|
|
"SNE.S {},RC.x,0;",
|
|
1u << index.U32(), ctx.reg_alloc.Define(inst));
|
|
}
|
|
|
|
void EmitIsImageScaled(EmitContext& ctx, IR::Inst& inst, const IR::Value& index) {
|
|
if (!index.IsImmediate()) {
|
|
throw NotImplementedException("Non-constant texture rescaling");
|
|
}
|
|
ctx.Add("AND.U RC.x,scaling[0].y,{};"
|
|
"SNE.S {},RC.x,0;",
|
|
1u << index.U32(), ctx.reg_alloc.Define(inst));
|
|
}
|
|
|
|
void EmitImageAtomicIAdd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "ADD.U32");
|
|
}
|
|
|
|
void EmitImageAtomicSMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarS32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "MIN.S32");
|
|
}
|
|
|
|
void EmitImageAtomicUMin32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "MIN.U32");
|
|
}
|
|
|
|
void EmitImageAtomicSMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarS32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "MAX.S32");
|
|
}
|
|
|
|
void EmitImageAtomicUMax32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "MAX.U32");
|
|
}
|
|
|
|
void EmitImageAtomicInc32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "IWRAP.U32");
|
|
}
|
|
|
|
void EmitImageAtomicDec32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "DWRAP.U32");
|
|
}
|
|
|
|
void EmitImageAtomicAnd32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "AND.U32");
|
|
}
|
|
|
|
void EmitImageAtomicOr32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "OR.U32");
|
|
}
|
|
|
|
void EmitImageAtomicXor32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index, Register coord,
|
|
ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "XOR.U32");
|
|
}
|
|
|
|
void EmitImageAtomicExchange32(EmitContext& ctx, IR::Inst& inst, const IR::Value& index,
|
|
Register coord, ScalarU32 value) {
|
|
ImageAtomic(ctx, inst, index, coord, value, "EXCH.U32");
|
|
}
|
|
|
|
void EmitBindlessImageSampleImplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageSampleExplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageSampleDrefImplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageSampleDrefExplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageGather(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageGatherDref(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageFetch(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageQueryDimensions(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageQueryLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageGradient(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageRead(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageWrite(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageSampleImplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageSampleExplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageSampleDrefImplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageSampleDrefExplicitLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageGather(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageGatherDref(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageFetch(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageQueryDimensions(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageQueryLod(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageGradient(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageRead(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageWrite(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicIAdd32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicSMin32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicUMin32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicSMax32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicUMax32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicInc32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicDec32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicAnd32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicOr32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicXor32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBindlessImageAtomicExchange32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicIAdd32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicSMin32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicUMin32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicSMax32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicUMax32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicInc32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicDec32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicAnd32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicOr32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicXor32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
void EmitBoundImageAtomicExchange32(EmitContext&) {
|
|
throw LogicError("Unreachable instruction");
|
|
}
|
|
|
|
} // namespace Shader::Backend::GLASM
|