73 lines
1.6 KiB
C++
73 lines
1.6 KiB
C++
// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <bitset>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Shader::IR {
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class Inst;
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class Value;
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} // namespace Shader::IR
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namespace Shader::Backend::GLSL {
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enum class Type : u32 {
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U32,
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S32,
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F32,
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U64,
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F64,
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Void,
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};
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struct Id {
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union {
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u32 raw;
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BitField<0, 29, u32> index;
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BitField<29, 1, u32> is_long;
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BitField<30, 1, u32> is_spill;
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BitField<31, 1, u32> is_condition_code;
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};
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bool operator==(Id rhs) const noexcept {
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return raw == rhs.raw;
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}
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bool operator!=(Id rhs) const noexcept {
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return !operator==(rhs);
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}
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};
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static_assert(sizeof(Id) == sizeof(u32));
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class RegAlloc {
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public:
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std::string Define(IR::Inst& inst, Type type = Type::Void);
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std::string Consume(const IR::Value& value);
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/// Returns true if the instruction is expected to be aliased to another
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static bool IsAliased(const IR::Inst& inst);
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/// Returns the underlying value out of an alias sequence
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static IR::Inst& AliasInst(IR::Inst& inst);
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private:
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static constexpr size_t NUM_REGS = 4096;
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static constexpr size_t NUM_ELEMENTS = 4;
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std::string Consume(IR::Inst& inst);
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std::string GetType(Type type, u32 index);
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Id Alloc();
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void Free(Id id);
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size_t num_used_registers{};
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std::bitset<NUM_REGS> register_use{};
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std::bitset<NUM_REGS> register_defined{};
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};
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} // namespace Shader::Backend::GLSL
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