Lioncash
387bffda5e
arm_interface: Remove unnecessary semicolon
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Namespaces don't require the use of a semicolon. Silences a -Wextra-semi
warning.
2018-12-30 20:41:33 -05:00
bunnei
331c252509
Merge pull request #1847 from ogniK5377/backtrace-break
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Print backtrace on svcBreak
2018-12-29 22:58:13 -05:00
David Marcec
22d4e10664
Moved log backtrace to arm_interface.cpp. Added printing of error code to fatal
2018-12-29 12:55:19 +11:00
David Marcec
08d5663cb8
Moved backtrace to ArmInterface
2018-12-19 14:10:51 +11:00
MerryMage
fd2c42bfcd
arm_dynarmic: Set CNTFRQ value
2018-12-18 17:28:12 +00:00
David Marcec
5102c91256
Moved backtrace to ArmInterface
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Added to both dynarmic and unicorn
2018-12-03 20:13:48 +11:00
Lioncash
aeadbfa790
core: Make the exclusive monitor a unique_ptr instead of a shared_ptr
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Like the barrier, this is owned entirely by the System and will always
outlive the encompassing state, so shared ownership semantics aren't
necessary here.
2018-10-15 14:15:50 -04:00
Lioncash
5c0408596f
kernel/thread: Use a regular pointer for the owner/current process
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There's no real need to use a shared pointer in these cases, and only
makes object management more fragile in terms of how easy it would be to
introduce cycles. Instead, just do the simple thing of using a regular
pointer. Much of this is just a hold-over from citra anyways.
It also doesn't make sense from a behavioral point of view for a
process' thread to prolong the lifetime of the process itself (the
process is supposed to own the thread, not the other way around).
2018-10-10 02:04:55 -04:00
Lioncash
baed7e1fba
kernel/thread: Make all instance variables private
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Many of the member variables of the thread class aren't even used
outside of the class itself, so there's no need to make those variables
public. This change follows in the steps of the previous changes that
made other kernel types' members private.
The main motivation behind this is that the Thread class will likely
change in the future as emulation becomes more accurate, and letting
random bits of the emulator access data members of the Thread class
directly makes it a pain to shuffle around and/or modify internals.
Having all data members public like this also makes it difficult to
reason about certain bits of behavior without first verifying what parts
of the core actually use them.
Everything being public also generally follows the tendency for changes
to be introduced in completely different translation units that would
otherwise be better introduced as an addition to the Thread class'
public interface.
2018-10-04 00:14:15 -04:00
Lioncash
cf9d6c6f52
kernel/process: Make data member variables private
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Makes the public interface consistent in terms of how accesses are done
on a process object. It also makes it slightly nicer to reason about the
logic of the process class, as we don't want to expose everything to
external code.
2018-09-30 02:30:01 -04:00
Lioncash
16145e2f21
arm_interface: Add missing fpsr/tpidr members to the ThreadContext struct
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Internally within the kernel, it also includes a member variable for the
floating-point status register, and TPIDR, so we should do the same here to match
it.
While we're at it, also fix up the size of the struct and add a static
assertion to ensure it always stays the correct size.
2018-09-30 02:29:57 -04:00
bunnei
f7b69d61f2
Merge pull request #1395 from lioncash/vm
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process/vm_manager: Initial modifications to load NPDM metadata
2018-09-29 10:54:39 -04:00
Lioncash
7fd598636e
memory: Dehardcode the use of a 36-bit address space
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Given games can also request a 32-bit or 39-bit address space, we
shouldn't be hardcoding the address space range as 36-bit.
2018-09-24 22:15:53 -04:00
Philippe Babin
fb6bc2c495
FPCR register was uninitialized at start up
2018-09-22 21:17:43 -04:00
Lioncash
9b8fc2b689
arm_interface: Replace kernel vm_manager include with a forward declaration
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Avoids an unnecessary inclusion and also uncovers three places where
indirect inclusions were relied upon, which allows us to also resolve
those.
2018-09-20 19:35:36 -04:00
MerryMage
ef31487624
arm_dynarmic: Halt when BRK encountered
2018-09-20 19:12:42 +01:00
MerryMage
3b4a158230
arm_dynarmic: Support BKPT instruction
2018-09-19 21:00:38 +01:00
bunnei
c2cf784376
Merge pull request #1344 from lioncash/arm
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arm_interface: Remove ARM11-isms from the CPU interface
2018-09-18 14:24:20 -04:00
Lioncash
ead2a4eeb4
arm_dynarmic: Correct ExclusiveWrite128()'s operation
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Previously the second half of the value being written would overwrite
the first half. Thankfully this wasn't a bug that was being encountered,
as the function is currently unused.
2018-09-18 03:56:32 -04:00
Lioncash
b51e7e0288
arm_interface: Remove ARM11-isms from the CPU interface
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This modifies the CPU interface to more accurately match an
AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods
don't even make sense to keep around for this interface, as Adv Simd is
used, rather than the VFP in the primary execution state. This is
essentially a modernization change that should have occurred from the
get-go.
2018-09-18 03:20:04 -04:00
fearlessTobi
63c2e32e20
Port #4182 from Citra: "Prefix all size_t with std::"
2018-09-15 15:21:06 +02:00
Markus Wick
10bc725944
Update microprofile scopes.
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Blame the subsystems which deserve the blame :)
The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
2018-09-04 11:04:26 +02:00
Lioncash
4a587b81b2
core/core: Replace includes with forward declarations where applicable
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The follow-up to e2457418da
2018-08-31 16:30:14 -04:00
Lioncash
43e0d865fa
core: Namespace all code in the arm subdirectory under the Core namespace
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Gets all of these types and interfaces out of the global namespace.
2018-08-24 21:50:39 -04:00
MerryMage
94329038b6
dynarmic: Update to 550d662
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550d662 load_store_exclusive: Define s == t state to be Constraint_NONE
0b69381 A64/translate: Allow for unpredictable behaviour to be defined
6d236d4 system: Implement MRS CNTFRQ_EL0
6cbb6fb A32/testenv: Add missing headers
6729328 externals: Update xbyak to v5.67
1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805
9a95802 externals: Document subtrees
714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants
8cab459 A64: Implement UQADD/UQSUB's scalar variants
18a8151 ir: Add opcodes for unsigned saturating add and subtract
a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo()
29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8>
e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR
55190bd fuzz_with_unicorn: Split utility functions into fuzz_util
23b049d A32/translate/load_store: Correct detection of writeback
7ec9f15 A32/translate: Add TranslateSingleInstruction
efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode
08d1d19 A32/decoders: Split instruction list into include file
2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn
f672368 microinstruction: Improve assert messages
7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation
edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
2018-08-16 10:12:20 +01:00
MerryMage
fcc5155601
arm_dynarmic: Remove IsExecuting check from PrepareReschedule
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No longer required. HaltExecution is a no-op if it is not currently executing.
2018-08-13 13:59:01 +01:00
Subv
d923766042
CPU/Timing: Use an approximated amortized amount of ticks when advancing timing.
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We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast.
This lets us bypass certain hangs in some games like Breath of the Wild.
We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
2018-08-12 20:41:28 -05:00
Hedges
e2b74f6354
GDBStub works with both Unicorn and Dynarmic now ( #941 )
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* GDBStub works with both Unicorn and Dynarmic now
* Tidy up
2018-08-06 22:01:24 -04:00
bunnei
f5efac3442
Merge pull request #876 from lioncash/include
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kernel: Remove unnecessary includes
2018-07-31 19:16:05 -07:00
Lioncash
a2304fad16
kernel: Remove unnecessary includes
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Removes unnecessary direct dependencies in some headers and also gets
rid of indirect dependencies that were being relied on to be included.
2018-07-31 10:15:17 -04:00
Lioncash
f08c0520a4
arm_dynarmic: Make SetTlsAddress() prototype and definition consistent
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Makes the definition use the same type aliases as in its prototype.
2018-07-31 07:58:26 -04:00
Lioncash
9d6aa7bff7
arm_dynarmic: Remove unnecessary qualifying of ThreadContext
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Given the ARM_Dynarmic class inherits from ARM_Interface, we don't need
to qualify here.
2018-07-31 07:56:59 -04:00
Lioncash
444a01afa6
arm_dynarmic: Correct initializer list order
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Amends the initializer list to be in the same order that each variable
would be initialized in. We also do this to ensure we don't use a bogus
uninitialized instance of the exclusive monitor within MakeJit()
We can also remove the jit member from the initializer list as this is
initialized by PageTableChanged()
2018-07-31 07:54:58 -04:00
Lioncash
7d124ec82b
arm_dynarmic: Make MakeJit() a const member function
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This functions doesn't modify instance state, so it can be a made a
const member function.
2018-07-23 23:19:37 -04:00
Lioncash
e12c84d5c5
exclusive_monitor: Use consistent type alias for u64
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Uses the same type aliases we use for virtual addresses, and converts
one lingering usage of std::array<uint64_t, 2> to u128 for consistency.
2018-07-23 20:54:57 -04:00
MerryMage
0b1c2e5505
Implement exclusive monitor
2018-07-22 15:55:17 +01:00
bunnei
de7cb91995
Merge pull request #750 from lioncash/ctx
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arm_interface: Remove unused tls_address member of ThreadContext
2018-07-21 11:38:16 -07:00
Subv
d84eb9dac6
CPU: Save and restore the TPIDR_EL0 system register on every context switch.
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Note that there's currently a dynarmic bug preventing this register from being written.
2018-07-20 19:57:45 -05:00
Lioncash
ae09adfcb3
arm_interface: Remove unused tls_address member of ThreadContext
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Currently, the TLS address is set within the scheduler, making this
member unused.
2018-07-20 18:57:40 -04:00
MerryMage
56cc1c11ec
scheduler: Clear exclusive state when switching contexts
2018-07-16 11:24:00 +01:00
Hedges
e066bc75b9
More improvements to GDBStub ( #653 )
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* More improvements to GDBStub
- Debugging of threads should work correctly with source and assembly level stepping and modifying registers and memory, meaning threads and callstacks are fully clickable in VS.
- List of modules is available to the client, with assumption that .nro and .nso are backed up by an .elf with symbols, while deconstructed ROMs keep N names.
- Initial support for floating point registers.
* Tidy up as requested in PR feedback
* Tidy up as requested in PR feedback
2018-07-12 20:22:59 -07:00
James Rowe
0d46f0df12
Update clang format
2018-07-02 21:45:47 -04:00
James Rowe
638956aa81
Rename logging macro back to LOG_*
2018-07-02 21:45:47 -04:00
Hedges
39fb3e362c
GDB Stub Improvements ( #508 )
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* GDB Stub should work now.
* Applied clang-format.
* Replaced htonll with swap64.
* Tidy up.
2018-06-06 00:20:47 -04:00
bunnei
a434fdcb10
core: Implement multicore support.
2018-05-10 19:34:46 -04:00
Lioncash
7c9644646f
general: Make formatting of logged hex values more straightforward
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This makes the formatting expectations more obvious (e.g. any zero padding specified
is padding that's entirely dedicated to the value being printed, not any pretty-printing
that also gets tacked on).
2018-05-02 09:49:36 -04:00
Lioncash
8475496630
general: Convert assertion macros over to be fmt-compatible
2018-04-27 10:04:02 -04:00
Lioncash
c33755e2b9
core: Replace remaining old non-generic logger usages with fmt-capable equivalents
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LOG_GENERIC usages will be amended in a follow-up to keep API changes separate from
interface changes, as it will require removing a parameter from the relevant function
in the VMManager class.
2018-04-26 15:37:16 -04:00
MerryMage
88c9608eac
arm_dynarmic: Fix timing
2018-03-24 09:02:19 +00:00
N00byKing
ef875d6a35
Clean Warnings (?)
2018-03-19 17:07:08 +01:00
bunnei
23a0d2d7b7
Merge pull request #193 from N00byKing/3184_2_robotic_boogaloo
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Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
2018-03-18 22:35:47 -04:00
bunnei
403f8e79ea
arm_interface: Support unmapping previously mapped memory.
2018-03-16 18:32:24 -04:00
bunnei
7d6653268f
core: Move process creation out of global state.
2018-03-14 18:42:19 -04:00
N00byKing
bc88cae0c7
Implements citra-emu/citra#3184
2018-02-25 11:44:21 +01:00
bunnei
c45173c9a6
Merge pull request #212 from mailwl/stubs
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Stub some functions
2018-02-23 21:09:56 -08:00
mailwl
910198a29a
Stub am::SetScreenShotPermission, and bsd::StartMonitoring functions
2018-02-22 13:04:23 +03:00
MerryMage
32d127ad3e
dynarmic: Update to 6b4c6b0
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6b4c6b0 impl: Update PC when raising exception
7a1313a A64: Implement FDIV (vector)
b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL
b277bf5 Correct FPSR and FPCR
7673933 A64: Implement USHL
8d0e558 A64: Implement UCVTF (vector, integer), scalar variant
da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point)
7479684 A64: Implement system register TPIDR_EL0
0fd75fd A64: Implement system registers FPCR and FPSR
31e370c A64: Implement system register CNTPCT_EL0
9a88fd3 A64: Implement system register CTR_EL0
1d16896 A64: Implement NEG (vector)
3184edf IR: Add IR instruction ZeroVector
31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter
567eb1a A64: Implement FMINNM (scalar)
c6d8fa1 A64: Implement FMAXNM (scalar)
616056d constant_pool: Add frame parameter
a3747cb A64: Implement ADDP (scalar)
5cd5d9f reg_alloc: Only exchange GPRs
dd0452a A64: Implement DUP (element), scalar variant
e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0
40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar)
7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect
826dce2 travis: Switch unicorn repository
9605f28 a64/config: Allow NaN emulation accuracy to be set
e9435bc a64_emit_x64: Add conf to A64EmitContext
30b596d fuzz_with_unicorn: Explicitly test floating point instructions
be292a8 A64: Implement FSQRT (scalar)
3c42d48 backend_x64: Accurately handle NaNs
4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
2018-02-21 21:39:07 +00:00
MerryMage
e8b9731af3
arm_dynarmic: LOG_INFO on unicorn fallback
2018-02-21 21:39:07 +00:00
MerryMage
6085d32cf5
arm_dynarmic: Support direct page table access
2018-02-12 21:53:32 +00:00
MerryMage
d3bbed5e78
dynarmic: Update to 41ae12263
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Changes: Primarily implementing more A64 instructions
2018-02-09 00:29:36 +00:00
River City Ransomware
dd62f125c3
Fixes some cast warnings, partial port of citra #3064 ( #106 )
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* Fixes some cast warnings, partially fixes citra #3064
* Converted casts to uint32_t to u32
* Ran clang-format
2018-01-19 18:01:41 -05:00
MerryMage
e35644c005
clang-format
2018-01-16 18:05:21 +00:00
James Rowe
2d7a85f7af
Build: Automagically handle unicorn
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On MSVC if unicorn isn't found, fallback to bundled unicorn
On everything else, fallback to building unicorn in externals
Also fixes loading unicorn in msvc
2018-01-16 09:39:07 -07:00
James Rowe
e026b66bbb
Build: Add unicorn as a submodule and build it if needed
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Adds a cmake custom target that will build unicorn on first compile and
uses this in the build scripts as well. Updates Appveyor and Travis
build scripts to work with the new unicorn build, and updates the paths
to all of the different artifacts.
2018-01-16 01:15:52 -07:00
MerryMage
668e5452fa
Update dynarmic to bc73004
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bc73004 a64_merge_interpret_blocks: Remove debug output
4e656ed tests/A64: Randomize PSTATE.<NZCV>
fd9530b A64: Optimization: Merge interpret blocks
3c9eb04 testenv: Use format constants
324f3fc tests/A64: Unicorn interface fixes
98ecbe7 tests/A64: Fuzz against unicorn
b1d38e7 tests/A64: Move TestEnvironment to own header
5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate
b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31
64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers
1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64
edadeea A64 inferface: Use two argument static_assert
9ab1304 A64: Add ExceptionRaised IR instruction
6843eed Update readme
7438d07 A64/translate: Add TranslateSingleInstruction function
2018-01-13 22:38:57 +00:00
bunnei
17af2937fe
arm_unicorn: Log unmapped memory access address.
2018-01-13 16:24:05 -05:00
bunnei
1247c53786
yuzu: Update license text to be consistent across project.
2018-01-13 16:22:39 -05:00
MerryMage
d2fbc78320
arm_dynarmic: Implement core
2018-01-12 17:48:29 -05:00
bunnei
b38223f662
arm_unicorn: Load/release unicorn DLL.
2018-01-04 13:40:01 -05:00
bunnei
3f8b9181b5
unicorn: Use for arm interface on Windows.
2018-01-04 00:13:23 -05:00
bunnei
6e9d66fd3a
arm_dynarmic: More cleanup.
2018-01-04 00:09:12 -05:00
bunnei
aa7e061e71
arm_dynarmic: Gut interface until dynarmic is ready for general use.
2018-01-03 22:10:11 -05:00
bunnei
b172f0d770
arm: Remove SkyEye/Dyncom code that is ARMv6-only.
2018-01-02 22:24:12 -05:00
bunnei
45db4bb3ea
logging: Rename category "Core_ARM11" to "Core_ARM".
2017-10-23 00:13:12 -04:00
bunnei
b1d5db1cf6
Merge remote-tracking branch 'upstream/master' into nx
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# Conflicts:
# src/core/CMakeLists.txt
# src/core/arm/dynarmic/arm_dynarmic.cpp
# src/core/arm/dyncom/arm_dyncom.cpp
# src/core/hle/kernel/process.cpp
# src/core/hle/kernel/thread.cpp
# src/core/hle/kernel/thread.h
# src/core/hle/kernel/vm_manager.cpp
# src/core/loader/3dsx.cpp
# src/core/loader/elf.cpp
# src/core/loader/ncch.cpp
# src/core/memory.cpp
# src/core/memory.h
# src/core/memory_setup.h
2017-10-09 23:56:20 -04:00
bunnei
6377585edb
arm_interface: Set TLS address for dynarmic core.
2017-09-30 14:34:03 -04:00
bunnei
3411883fe3
arm: Use 64-bit addressing in a bunch of places.
2017-09-30 14:28:53 -04:00
Huw Pascoe
529f4a0131
Moved down_count to CoreTiming
2017-09-30 17:38:14 +01:00
MerryMage
67a70bd9e1
ARM_Interface: Implement PageTableChanged
2017-09-24 23:08:25 +01:00
B3n30
813837c5cf
Merge pull request #2842 from Subv/switchable_page_table
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Kernel/Memory: Give each process its own page table and allow switching the current page table upon reschedule
2017-09-15 22:41:45 +02:00
Subv
7a3ab7c63d
CPU/Dynarmic: Disable the fast page-table access in dynarmic until it supports switching page tables at runtime.
2017-09-15 14:26:22 -05:00
Subv
d237a89048
CPU/Dynarmic: Fixed a warning when incrementing the number of ticks in ExecuteInstructions.
2017-08-21 08:34:25 -05:00
Subv
9d0841b48b
Dyncom: Use size_t instead of int to store the instruction offsets in the instruction cache.
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Fixes a few warnings.
2017-08-21 08:34:23 -05:00
Subv
d3fb1d6c38
Dyncom: Fixed a conversion warning when decoding thumb instructions.
2017-08-21 08:20:36 -05:00
Sebastian Valle
c291db72e7
Merge pull request #2692 from Subv/vfp_ftz
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Dyncom/VFP: Convert denormal outputs into 0 when the FTZ flag is enabled.
2017-05-22 12:16:53 -05:00
Subv
5b46a89230
fixup! Dyncom/VFP: Convert denormal outputs into 0 when the FTZ flag is enabled.
2017-05-21 18:56:09 -05:00
Merry
188d63fdb6
Merge pull request #2694 from Subv/vfp_vsub_ftz
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Dyncom/VFP: Perform flush-to-zero on the second operand of vsub before sending it to vadd.
2017-05-22 00:50:52 +01:00
Subv
a0874a7a68
Dyncom/VFP: Perform flush-to-zero on the second operand of vsub before sending it to vadd.
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Previously we were letting vadd flush the value to positive 0, but there are cases where this behavior is wrong, for example,
vsub: -0 - +0 = -0
vadd: -0 + +0 = +0
Now we'll flush the value to +0 inside vsub, and then negate it.
2017-05-13 18:03:41 -05:00
Yuri Kunde Schlesner
13dd0b88de
Merge pull request #2696 from Subv/vfp_revert
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Dyncom/VFP: Revert edf30d8
2017-05-08 21:38:45 -07:00
Subv
11fe85f129
Dyncom/VFP: Strip the VFP_NAN_FLAG sentinel value when setting vfp exceptions.
2017-05-09 00:36:23 -05:00
Subv
bf45ccfb40
Revert "Remove exceptions parameter from normaliseround VFP functions"
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This reverts commit edf30d84cc
2017-05-09 00:36:22 -05:00
Subv
b1a29371c9
Dyncom/VFP: Convert denormal outputs into 0 when the FTZ flag is enabled.
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Inputs are still not flushed to 0 if they are denormals.
2017-05-08 14:34:16 -05:00
Yuri Kunde Schlesner
d97b977540
Dyncom: Remove disassembler code
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Had licensing issue around it, in addition to several bugs.
Closes #1632 , #1280
2017-05-07 15:33:46 -07:00
Yuri Kunde Schlesner
f0a582b218
Dyncom: Tweak types and log formatting
2017-05-07 15:33:42 -07:00
Yuri Kunde Schlesner
cb4da3975e
Remove unused symbols code
2017-05-07 15:33:39 -07:00
MerryMage
b125388152
dyncom: Correct SXTAB16 and SXTB16
2017-02-18 20:04:54 +00:00
MerryMage
e2815408fd
arm_dynarmic: Update memory interface
2017-02-03 17:32:51 +00:00
MerryMage
2b36d4c9d7
arm_dynarmic: CP15 support
2017-02-03 17:32:47 +00:00
bunnei
76890672a0
Merge pull request #2366 from MerryMage/MemoryReadCode
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arm_dynarmic: Provide MemoryReadCode callback
2016-12-22 14:25:15 -05:00
MerryMage
f8cf87ce34
arm_dynarmic: Provide MemoryReadCode callback
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Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
2016-12-22 16:07:14 +00:00
bunnei
8b1e269e58
ThreadContext: Move from "core" to "arm_interface".
2016-12-22 00:27:49 -05:00
Lioncash
ba20dd9b61
gdbstub: Remove global variable from public interface
...
Currently, this is only ever queried, so adding a function to check if the
server is enabled is more sensible.
If directly modifying this externally is ever desirable, it should be done
by adding a function to the interface, rather than exposing implementation
details directly.
2016-12-15 16:37:22 -05:00
Lioncash
2f3c1bdfb4
core: Add missing #pragma once directives where applicable
2016-12-15 15:40:51 -05:00
Emmanuel Gil Peyrot
643e590b5c
Core: Add a forgotten #include <cstring> for memcpy.
2016-12-11 01:20:45 +00:00
MerryMage
27be446049
dynarmic: Add ticks based on ticks executed, not ticks requested
2016-11-26 20:32:33 +00:00
James Rowe
bbe57a66ca
Expose page table to dynarmic for optimized reads and writes to the JIT
2016-11-24 20:41:18 -07:00
Yuri Kunde Schlesner
84fbbe2629
Use negative priorities to avoid special-casing the self-include
2016-09-21 00:15:56 -07:00
Emmanuel Gil Peyrot
ebdae19fd2
Remove empty newlines in #include blocks.
...
This makes clang-format useful on those.
Also add a bunch of forgotten transitive includes, which otherwise
prevented compilation.
2016-09-21 11:15:47 +09:00
Yuri Kunde Schlesner
396a8d91a4
Manually tweak source formatting and then re-run clang-format
2016-09-18 21:14:25 -07:00
Emmanuel Gil Peyrot
dc8479928c
Sources: Run clang-format on everything.
2016-09-18 09:38:01 +09:00
Emmanuel Gil Peyrot
bfc454e951
Dyncom: Disable clang-format on the decoding table.
2016-09-18 09:36:57 +09:00
bunnei
1b95f61d82
arm_dynarmic: Implement GetVFPSystemReg/SetVFPSystemReg.
2016-09-15 17:58:06 -04:00
bunnei
05e120a4cc
arm: ResetContext shouldn't be part of ARM_Interface.
2016-09-15 17:49:30 -04:00
bunnei
85861d44b7
arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.
2016-09-15 17:49:30 -04:00
bunnei
b7aef81cb4
dyncom: Use VFP_FPSCR/VFP_FPEXC.
2016-09-15 17:49:29 -04:00
bunnei
1976a2d773
dynarmic: Implement ARM CPU interface.
2016-09-15 17:49:26 -04:00
wwylele
2161f52661
ARM: add ClearInstructionCache function
2016-08-27 21:38:06 +08:00
MerryMage
15b2eec4bd
dyncom: Read-after-write in SMLA
...
In the case when RD === RN, RD was updated before AddOverflow was called
to check for an overflow, resulting in an incorrect state of the Q flag.
2016-08-22 15:13:33 +01:00
MerryMage
50407a8dc8
Dyncom: Correct implementation of STM for R15
2016-08-14 00:49:34 +01:00
MerryMage
60c93ca3b5
dyncom: Fix translation of thumb REVSH
2016-07-28 11:51:29 +01:00
archshift
ca20b1f87d
Make arm_dyncom_trans* into a fully fledged compilation unit
2016-06-12 01:54:45 -07:00
archshift
54b5178f6c
arm_dyncom_interpreter: slightly change AllocBuffer to be intuitive
2016-06-12 00:31:52 -07:00
archshift
765eef3319
arm_dyncom_interpreter: Add specialized GetAddressingOpLoadStoreT func
...
This allows us to get the addressing operation for STRT, LDRT, STRBT,
and LDRBT. We do this so that translation functions don't need to
see the addressing ops directly.
2016-06-10 18:45:48 -07:00
archshift
eac4c016cb
arm_dyncom_interpreter: rename operation functions to fit style guide
2016-06-10 18:42:08 -07:00
archshift
5297f5dfc9
arm_dyncom_interpreter: Rename anonymous enum to TransExtData
2016-06-10 18:35:57 -07:00
archshift
2c482722e7
arm_dyncom_interpreter.cpp: #include translation info from inc files
2016-06-10 18:25:30 -07:00
Mat M
031a9c57bb
Merge pull request #1568 from JayFoxRox/fix-printf
...
Fix ftoi and disable VFPv3
2016-05-26 19:03:00 -04:00
Jannik Vogel
edf30d84cc
Remove exceptions parameter from normaliseround VFP functions
2016-05-18 16:28:13 +02:00
Jannik Vogel
693cca8f1f
Fix exception propagation for VFP single precision
2016-05-18 15:24:42 +02:00
Jannik Vogel
7dde13f875
Fix exception propagation for VFP double precision
2016-05-18 15:24:42 +02:00
Jannik Vogel
3a45eacb16
Fix read-after-write in SMUAD, SMLAD, SMUSD, SMLSD
2016-05-18 14:03:02 +02:00
Jannik Vogel
af37dd0d52
Set fpscr for new threads
2016-05-17 08:59:52 +02:00
Jannik Vogel
501d0bc5ed
Fix ftoi behaviour
2016-05-16 15:00:45 +02:00
Jannik Vogel
6fe0cb671d
Respect fpscr in ftoiz
2016-05-16 15:00:45 +02:00
Jannik Vogel
1643786c04
Disable VFP3 instructions
2016-05-16 15:00:45 +02:00
Lioncash
0f941d0245
dyncom: Reset the context into user mode correctly
...
The other mode was system mode.
2016-05-09 16:30:55 -04:00
Yuri Kunde Schlesner
e3a8292495
Common: Remove section measurement from profiler ( #1731 )
...
This has been entirely superseded by MicroProfile. The rest of the code
can go when a simpler frametime/FPS meter is added to the GUI.
2016-04-29 00:07:10 -07:00
mailwl
2efc1c9348
Fix BLX LR opcode interpretation
2016-04-09 19:11:02 +03:00
mailwl
4630209c4c
Update cpsr (T)humb bit while creating thread
2016-04-08 18:41:09 +03:00
mailwl
06a4369f75
Fix thumb ADR instruction alignment
2016-04-06 19:46:58 +03:00
Mathew Maidment
aa6380e5bc
Merge pull request #1643 from MerryMage/make_unique
...
Common: Remove Common::make_unique, use std::make_unique
2016-04-05 20:10:11 -04:00
MerryMage
a06dcfeb61
Common: Remove Common::make_unique, use std::make_unique
2016-04-05 13:31:17 +01:00
Mathew Maidment
80c16961ae
Merge pull request #1618 from MerryMage/one-step
...
Prevent cache overflow when single stepping
2016-03-31 11:00:42 -04:00
MerryMage
cbba0bec7c
DynCom: Optimize single stepping
2016-03-30 18:57:59 +01:00
Lioncash
d53c9cde1a
armstate: Correct FIQ register banking
...
FIQ has seven banked registers (R8 to R14), not two.
2016-03-21 18:56:27 -04:00
rob turner
d29578d467
ARM_Disasm::DisassembleMemHalf: actually use width in determining opcode name
2016-01-19 18:42:16 +01:00
Lioncash
532dc797c9
arm_dyncom_dec: Fix decoding of VMLS
...
Previously, all VMLS variants would misdecode as CDP
(which isn't necessarily wrong in itself, however
VMLS has it's own label of execution)
2015-12-30 14:23:07 -05:00
Lioncash
fddfe946c8
dyncom: Handle modifying the APSR via an MRC instruction
2015-12-28 07:52:04 -05:00
Lioncash
d09b7a3c12
dyncom: Remove PC dispatch from several instructions
...
These instructions aren't capable of using the PC as a destination
2015-12-20 21:19:02 -05:00
Lioncash
5a531d7ec2
dyncom: Handle unprivileged load/store variants correctly
...
LDRT/LDRBT/STRBT/STRT should simulate the load or store
as if the host CPU is in user mode.
STRT is also allowed to use the PC as an operand
2015-12-19 19:05:50 -05:00
