engines/maxwell_3d: Add TFB registers and store them in shader registry
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@ -67,6 +67,7 @@ public:
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static constexpr std::size_t NumVaryings = 31;
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static constexpr std::size_t NumVaryings = 31;
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static constexpr std::size_t NumImages = 8; // TODO(Rodrigo): Investigate this number
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static constexpr std::size_t NumImages = 8; // TODO(Rodrigo): Investigate this number
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static constexpr std::size_t NumClipDistances = 8;
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static constexpr std::size_t NumClipDistances = 8;
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static constexpr std::size_t NumTransformFeedbackBuffers = 4;
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static constexpr std::size_t MaxShaderProgram = 6;
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static constexpr std::size_t MaxShaderProgram = 6;
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static constexpr std::size_t MaxShaderStage = 5;
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static constexpr std::size_t MaxShaderStage = 5;
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// Maximum number of const buffers per shader stage.
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// Maximum number of const buffers per shader stage.
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@ -621,6 +622,22 @@ public:
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float depth_range_far;
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float depth_range_far;
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};
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};
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struct alignas(32) TransformFeedbackBinding {
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u32 buffer_enable;
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u32 address_high;
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u32 address_low;
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s32 buffer_size;
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s32 buffer_offset;
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};
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static_assert(sizeof(TransformFeedbackBinding) == 32);
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struct alignas(16) TransformFeedbackLayout {
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u32 stream;
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u32 varying_count;
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u32 stride;
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};
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static_assert(sizeof(TransformFeedbackLayout) == 16);
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bool IsShaderConfigEnabled(std::size_t index) const {
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bool IsShaderConfigEnabled(std::size_t index) const {
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// The VertexB is always enabled.
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// The VertexB is always enabled.
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if (index == static_cast<std::size_t>(Regs::ShaderProgram::VertexB)) {
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if (index == static_cast<std::size_t>(Regs::ShaderProgram::VertexB)) {
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@ -677,7 +694,13 @@ public:
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u32 rasterize_enable;
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u32 rasterize_enable;
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INSERT_UNION_PADDING_WORDS(0xF1);
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std::array<TransformFeedbackBinding, NumTransformFeedbackBuffers> tfb_bindings;
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INSERT_UNION_PADDING_WORDS(0xC0);
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std::array<TransformFeedbackLayout, NumTransformFeedbackBuffers> tfb_layouts;
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INSERT_UNION_PADDING_WORDS(0x1);
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u32 tfb_enabled;
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u32 tfb_enabled;
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@ -1187,7 +1210,11 @@ public:
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u32 tex_cb_index;
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u32 tex_cb_index;
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INSERT_UNION_PADDING_WORDS(0x395);
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INSERT_UNION_PADDING_WORDS(0x7D);
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std::array<std::array<u8, 128>, NumTransformFeedbackBuffers> tfb_varying_locs;
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INSERT_UNION_PADDING_WORDS(0x298);
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struct {
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struct {
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/// Compressed address of a buffer that holds information about bound SSBOs.
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/// Compressed address of a buffer that holds information about bound SSBOs.
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@ -1413,6 +1440,8 @@ ASSERT_REG_POSITION(tess_mode, 0xC8);
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ASSERT_REG_POSITION(tess_level_outer, 0xC9);
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ASSERT_REG_POSITION(tess_level_outer, 0xC9);
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ASSERT_REG_POSITION(tess_level_inner, 0xCD);
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ASSERT_REG_POSITION(tess_level_inner, 0xCD);
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ASSERT_REG_POSITION(rasterize_enable, 0xDF);
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ASSERT_REG_POSITION(rasterize_enable, 0xDF);
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ASSERT_REG_POSITION(tfb_bindings, 0xE0);
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ASSERT_REG_POSITION(tfb_layouts, 0x1C0);
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ASSERT_REG_POSITION(tfb_enabled, 0x1D1);
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ASSERT_REG_POSITION(tfb_enabled, 0x1D1);
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(viewport_transform, 0x280);
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ASSERT_REG_POSITION(viewport_transform, 0x280);
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@ -1508,6 +1537,7 @@ ASSERT_REG_POSITION(firmware, 0x8C0);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(tfb_varying_locs, 0xA00);
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ASSERT_REG_POSITION(ssbo_info, 0xD18);
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ASSERT_REG_POSITION(ssbo_info, 0xD18);
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ASSERT_REG_POSITION(tex_info_buffers.address[0], 0xD2A);
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ASSERT_REG_POSITION(tex_info_buffers.address[0], 0xD2A);
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ASSERT_REG_POSITION(tex_info_buffers.size[0], 0xD2F);
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ASSERT_REG_POSITION(tex_info_buffers.size[0], 0xD2F);
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@ -48,7 +48,7 @@ struct BindlessSamplerKey {
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Tegra::Engines::SamplerDescriptor sampler;
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Tegra::Engines::SamplerDescriptor sampler;
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};
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};
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constexpr u32 NativeVersion = 19;
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constexpr u32 NativeVersion = 20;
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ShaderCacheVersionHash GetShaderCacheVersionHash() {
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ShaderCacheVersionHash GetShaderCacheVersionHash() {
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ShaderCacheVersionHash hash{};
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ShaderCacheVersionHash hash{};
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@ -27,9 +27,12 @@ GraphicsInfo MakeGraphicsInfo(ShaderType shader_stage, ConstBufferEngineInterfac
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auto& graphics = static_cast<Tegra::Engines::Maxwell3D&>(engine);
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auto& graphics = static_cast<Tegra::Engines::Maxwell3D&>(engine);
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GraphicsInfo info;
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GraphicsInfo info;
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info.tfb_layouts = graphics.regs.tfb_layouts;
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info.tfb_varying_locs = graphics.regs.tfb_varying_locs;
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info.primitive_topology = graphics.regs.draw.topology;
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info.primitive_topology = graphics.regs.draw.topology;
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info.tessellation_primitive = graphics.regs.tess_mode.prim;
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info.tessellation_primitive = graphics.regs.tess_mode.prim;
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info.tessellation_spacing = graphics.regs.tess_mode.spacing;
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info.tessellation_spacing = graphics.regs.tess_mode.spacing;
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info.tfb_enabled = graphics.regs.tfb_enabled;
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info.tessellation_clockwise = graphics.regs.tess_mode.cw;
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info.tessellation_clockwise = graphics.regs.tess_mode.cw;
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return info;
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return info;
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}
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}
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@ -25,9 +25,15 @@ using BindlessSamplerMap =
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std::unordered_map<std::pair<u32, u32>, Tegra::Engines::SamplerDescriptor, Common::PairHash>;
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std::unordered_map<std::pair<u32, u32>, Tegra::Engines::SamplerDescriptor, Common::PairHash>;
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struct GraphicsInfo {
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struct GraphicsInfo {
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Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology primitive_topology{};
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using Maxwell = Tegra::Engines::Maxwell3D::Regs;
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Tegra::Engines::Maxwell3D::Regs::TessellationPrimitive tessellation_primitive{};
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Tegra::Engines::Maxwell3D::Regs::TessellationSpacing tessellation_spacing{};
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std::array<Maxwell::TransformFeedbackLayout, Maxwell::NumTransformFeedbackBuffers>
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tfb_layouts{};
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std::array<std::array<u8, 128>, Maxwell::NumTransformFeedbackBuffers> tfb_varying_locs{};
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Maxwell::PrimitiveTopology primitive_topology{};
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Maxwell::TessellationPrimitive tessellation_primitive{};
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Maxwell::TessellationSpacing tessellation_spacing{};
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bool tfb_enabled = false;
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bool tessellation_clockwise = false;
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bool tessellation_clockwise = false;
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};
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};
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static_assert(std::is_trivially_copyable_v<GraphicsInfo> &&
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static_assert(std::is_trivially_copyable_v<GraphicsInfo> &&
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