shader_ir/conversion: Implement F2I F16 Ra.H1
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b4a8cfbd00
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@ -1006,7 +1006,7 @@ union Instruction {
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} iset;
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} iset;
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union {
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union {
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BitField<41, 2, u64> selector; // i2i and i2f only
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BitField<41, 2, u64> selector;
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BitField<45, 1, u64> negate_a;
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BitField<45, 1, u64> negate_a;
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BitField<49, 1, u64> abs_a;
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BitField<49, 1, u64> abs_a;
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BitField<10, 2, Register::Size> src_size;
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BitField<10, 2, Register::Size> src_size;
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@ -1031,7 +1031,6 @@ union Instruction {
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return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
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return static_cast<F2fRoundingOp>(rounding.Value() & rounding_mask);
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}
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}
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} f2f;
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} f2f;
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} conversion;
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} conversion;
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union {
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union {
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@ -22,7 +22,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_IMM: {
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case OpCode::Id::I2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF(instr.conversion.selector.Value());
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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@ -57,8 +57,8 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_C:
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case OpCode::Id::I2F_IMM: {
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case OpCode::Id::I2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.selector.Value());
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.selector);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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"Condition codes generation in I2F is not implemented");
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"Condition codes generation in I2F is not implemented");
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@ -93,6 +93,7 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::F2F_R:
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case OpCode::Id::F2F_R:
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_C:
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case OpCode::Id::F2F_IMM: {
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case OpCode::Id::F2F_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.selector.Value());
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.dst_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF(instr.conversion.src_size == Register::Size::Long);
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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UNIMPLEMENTED_IF_MSG(instr.generates_cc,
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@ -169,8 +170,19 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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}();
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}();
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if (instr.conversion.src_size == Register::Size::Short) {
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if (instr.conversion.src_size == Register::Size::Short) {
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// TODO: figure where extract is sey in the encoding
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const OperationCode cast = [instr] {
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value = Operation(OperationCode::FCastHalf0, PRECISE, value);
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switch (instr.conversion.selector) {
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case 0:
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return OperationCode::FCastHalf0;
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case 1:
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return OperationCode::FCastHalf1;
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default:
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UNREACHABLE_MSG("Invalid selector={}",
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static_cast<u32>(instr.conversion.selector));
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return OperationCode::FCastHalf0;
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}
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}();
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value = Operation(cast, NO_PRECISE, std::move(value));
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}
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}
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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value = GetOperandAbsNegFloat(value, instr.conversion.abs_a, instr.conversion.negate_a);
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