core: arm_dynarmic_32: Update SaveContext/LoadContext.

This commit is contained in:
bunnei 2023-04-01 17:03:08 -07:00
parent 2ddecb9631
commit 9c94faaa2b

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@ -5,7 +5,6 @@
#include <memory> #include <memory>
#include <dynarmic/interface/A32/a32.h> #include <dynarmic/interface/A32/a32.h>
#include <dynarmic/interface/A32/config.h> #include <dynarmic/interface/A32/config.h>
#include <dynarmic/interface/A32/context.h>
#include "common/assert.h" #include "common/assert.h"
#include "common/literals.h" #include "common/literals.h"
#include "common/logging/log.h" #include "common/logging/log.h"
@ -410,21 +409,19 @@ void ARM_Dynarmic_32::SetTPIDR_EL0(u64 value) {
} }
void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) { void ARM_Dynarmic_32::SaveContext(ThreadContext32& ctx) {
Dynarmic::A32::Context context; Dynarmic::A32::Jit* j = jit.load();
jit.load()->SaveContext(context); ctx.cpu_registers = j->Regs();
ctx.cpu_registers = context.Regs(); ctx.extension_registers = j->ExtRegs();
ctx.extension_registers = context.ExtRegs(); ctx.cpsr = j->Cpsr();
ctx.cpsr = context.Cpsr(); ctx.fpscr = j->Fpscr();
ctx.fpscr = context.Fpscr();
} }
void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) { void ARM_Dynarmic_32::LoadContext(const ThreadContext32& ctx) {
Dynarmic::A32::Context context; Dynarmic::A32::Jit* j = jit.load();
context.Regs() = ctx.cpu_registers; j->Regs() = ctx.cpu_registers;
context.ExtRegs() = ctx.extension_registers; j->ExtRegs() = ctx.extension_registers;
context.SetCpsr(ctx.cpsr); j->SetCpsr(ctx.cpsr);
context.SetFpscr(ctx.fpscr); j->SetFpscr(ctx.fpscr);
jit.load()->LoadContext(context);
} }
void ARM_Dynarmic_32::SignalInterrupt() { void ARM_Dynarmic_32::SignalInterrupt() {