Add memory Layout to Render Targets and Depth Buffers
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@ -347,6 +347,16 @@ public:
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DecrWrap = 8,
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};
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enum class MemoryLayout : u32 {
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Linear = 0,
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BlockLinear = 1,
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};
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enum class InvMemoryLayout : u32 {
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BlockLinear = 0,
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Linear = 1,
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};
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struct Cull {
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enum class FrontFace : u32 {
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ClockWise = 0x0900,
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@ -436,7 +446,8 @@ public:
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BitField<0, 3, u32> block_width;
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BitField<4, 3, u32> block_height;
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BitField<8, 3, u32> block_depth;
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} block_dimensions;
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BitField<12, 1, InvMemoryLayout> type;
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} memory_layout;
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u32 array_mode;
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u32 layer_stride;
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u32 base_layer;
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@ -556,7 +567,8 @@ public:
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BitField<0, 4, u32> block_width;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_depth;
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} block_dimensions;
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BitField<20, 1, InvMemoryLayout> type;
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} memory_layout;
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u32 layer_stride;
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GPUVAddr Address() const {
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@ -99,10 +99,11 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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const auto& config{Core::System::GetInstance().GPU().Maxwell3D().regs.rt[index]};
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(config.Address());
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params.is_tiled = true;
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params.block_width = 1 << config.block_dimensions.block_width;
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params.block_height = 1 << config.block_dimensions.block_height;
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params.block_depth = 1 << config.block_dimensions.block_depth;
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params.is_tiled =
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config.memory_layout.type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_width = 1 << config.memory_layout.block_width;
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params.block_height = 1 << config.memory_layout.block_height;
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params.block_depth = 1 << config.memory_layout.block_depth;
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params.pixel_format = PixelFormatFromRenderTargetFormat(config.format);
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params.component_type = ComponentTypeFromRenderTarget(config.format);
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params.type = GetFormatType(params.pixel_format);
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@ -124,14 +125,13 @@ static VAddr TryGetCpuAddr(Tegra::GPUVAddr gpu_addr) {
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return params;
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}
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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Tegra::GPUVAddr zeta_address,
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Tegra::DepthFormat format,
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u32 block_width, u32 block_height,
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u32 block_depth) {
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/*static*/ SurfaceParams SurfaceParams::CreateForDepthBuffer(
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u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
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u32 block_width, u32 block_height, u32 block_depth,
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Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type) {
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SurfaceParams params{};
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params.addr = TryGetCpuAddr(zeta_address);
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params.is_tiled = true;
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params.is_tiled = type == Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout::BlockLinear;
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params.block_width = 1 << std::min(block_width, 5U);
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params.block_height = 1 << std::min(block_height, 5U);
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params.block_depth = 1 << std::min(block_depth, 5U);
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@ -1005,8 +1005,8 @@ Surface RasterizerCacheOpenGL::GetDepthBufferSurface(bool preserve_contents) {
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SurfaceParams depth_params{SurfaceParams::CreateForDepthBuffer(
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regs.zeta_width, regs.zeta_height, regs.zeta.Address(), regs.zeta.format,
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regs.zeta.block_dimensions.block_width, regs.zeta.block_dimensions.block_height,
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regs.zeta.block_dimensions.block_depth)};
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regs.zeta.memory_layout.block_width, regs.zeta.memory_layout.block_height,
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regs.zeta.memory_layout.block_depth, regs.zeta.memory_layout.type)};
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return GetSurface(depth_params, preserve_contents);
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}
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@ -716,10 +716,10 @@ struct SurfaceParams {
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static SurfaceParams CreateForFramebuffer(std::size_t index);
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/// Creates SurfaceParams for a depth buffer configuration
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static SurfaceParams CreateForDepthBuffer(u32 zeta_width, u32 zeta_height,
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Tegra::GPUVAddr zeta_address,
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Tegra::DepthFormat format, u32 block_width,
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u32 block_height, u32 block_depth);
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static SurfaceParams CreateForDepthBuffer(
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u32 zeta_width, u32 zeta_height, Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format,
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u32 block_width, u32 block_height, u32 block_depth,
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Tegra::Engines::Maxwell3D::Regs::InvMemoryLayout type);
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/// Creates SurfaceParams for a Fermi2D surface copy
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static SurfaceParams CreateForFermiCopySurface(
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