Merge pull request #2103 from wwylele/gpu-reg-cleanup

GPU: DisplayTransfer & MemoryFill cleanup and param check

src/core/hw/gpu.cpp

@@ -80,31 +80,28 @@ static Math::Vec4<u8> DecodePixel(Regs::PixelFormat input_format, const u8* src_
 MICROPROFILE_DEFINE(GPU_DisplayTransfer, "GPU", "DisplayTransfer", MP_RGB(100, 100, 255));
 MICROPROFILE_DEFINE(GPU_CmdlistProcessing, "GPU", "Cmdlist Processing", MP_RGB(100, 255, 100));
 
-template <typename T>
+static void MemoryFill(const Regs::MemoryFillConfig& config) {
-inline void Write(u32 addr, const T data) {
+    const PAddr start_addr = config.GetStartAddress();
-    addr -= HW::VADDR_GPU;
+    const PAddr end_addr = config.GetEndAddress();
-    u32 index = addr / 4;
 
-    // Writes other than u32 are untested, so I'd rather have them abort than silently fail
+    // TODO: do hwtest with these cases
-    if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
+    if (!Memory::IsValidPhysicalAddress(start_addr)) {
-        LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
+        LOG_CRITICAL(HW_GPU, "invalid start address 0x%08X", start_addr);
         return;
     }
 
-    g_regs[index] = static_cast<u32>(data);
+    if (!Memory::IsValidPhysicalAddress(end_addr)) {
+        LOG_CRITICAL(HW_GPU, "invalid end address 0x%08X", end_addr);
+        return;
+    }
 
-    switch (index) {
+    if (end_addr <= start_addr) {
+        LOG_CRITICAL(HW_GPU, "invalid memory range from 0x%08X to 0x%08X", start_addr, end_addr);
+        return;
+    }
 
-    // Memory fills are triggered once the fill value is written.
+    u8* start = Memory::GetPhysicalPointer(start_addr);
-    case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
+    u8* end = Memory::GetPhysicalPointer(end_addr);
-    case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
-        const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
-        auto& config = g_regs.memory_fill_config[is_second_filler];
-
-        if (config.trigger) {
-            if (config.address_start) { // Some games pass invalid values here
-                u8* start = Memory::GetPhysicalPointer(config.GetStartAddress());
-                u8* end = Memory::GetPhysicalPointer(config.GetEndAddress());
 
     // TODO: Consider always accelerating and returning vector of
     //       regions that the accelerated fill did not cover to
@@ -115,10 +112,11 @@ inline void Write(u32 addr, const T data) {
     //       Then fill all completely covered surfaces, and return the
     //       regions that were between surfaces or within the touching
     //       ones for cpu to manually fill here.
-                if (!VideoCore::g_renderer->Rasterizer()->AccelerateFill(config)) {
+    if (VideoCore::g_renderer->Rasterizer()->AccelerateFill(config))
+        return;
+
     Memory::RasterizerFlushAndInvalidateRegion(config.GetStartAddress(),
-                                                               config.GetEndAddress() -
+                                               config.GetEndAddress() - config.GetStartAddress());
-                                                                   config.GetStartAddress());
 
     if (config.fill_24bit) {
         // fill with 24-bit values
@@ -141,104 +139,60 @@ inline void Write(u32 addr, const T data) {
         for (u8* ptr = start; ptr < end; ptr += sizeof(u16))
             memcpy(ptr, &value_16bit, sizeof(u16));
     }
+}
+
+static void DisplayTransfer(const Regs::DisplayTransferConfig& config) {
+    const PAddr src_addr = config.GetPhysicalInputAddress();
+    const PAddr dst_addr = config.GetPhysicalOutputAddress();
+
+    // TODO: do hwtest with these cases
+    if (!Memory::IsValidPhysicalAddress(src_addr)) {
+        LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
+        return;
     }
 
-                LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
+    if (!Memory::IsValidPhysicalAddress(dst_addr)) {
-                          config.GetEndAddress());
+        LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
-
+        return;
-                if (!is_second_filler) {
-                    GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
-                } else {
-                    GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
-                }
     }
 
-            // Reset "trigger" flag and set the "finish" flag
+    if (config.input_width == 0) {
-            // NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
+        LOG_CRITICAL(HW_GPU, "zero input width");
-            config.trigger.Assign(0);
+        return;
-            config.finished.Assign(1);
-        }
-        break;
     }
 
-    case GPU_REG_INDEX(display_transfer_config.trigger): {
+    if (config.input_height == 0) {
-        MICROPROFILE_SCOPE(GPU_DisplayTransfer);
+        LOG_CRITICAL(HW_GPU, "zero input height");
-
+        return;
-        const auto& config = g_regs.display_transfer_config;
-        if (config.trigger & 1) {
-
-            if (Pica::g_debug_context)
-                Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
-                                               nullptr);
-
-            if (!VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config)) {
-                u8* src_pointer = Memory::GetPhysicalPointer(config.GetPhysicalInputAddress());
-                u8* dst_pointer = Memory::GetPhysicalPointer(config.GetPhysicalOutputAddress());
-
-                if (config.is_texture_copy) {
-                    u32 input_width = config.texture_copy.input_width * 16;
-                    u32 input_gap = config.texture_copy.input_gap * 16;
-                    u32 output_width = config.texture_copy.output_width * 16;
-                    u32 output_gap = config.texture_copy.output_gap * 16;
-
-                    size_t contiguous_input_size =
-                        config.texture_copy.size / input_width * (input_width + input_gap);
-                    Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
-                                                  static_cast<u32>(contiguous_input_size));
-
-                    size_t contiguous_output_size =
-                        config.texture_copy.size / output_width * (output_width + output_gap);
-                    Memory::RasterizerFlushAndInvalidateRegion(
-                        config.GetPhysicalOutputAddress(),
-                        static_cast<u32>(contiguous_output_size));
-
-                    u32 remaining_size = config.texture_copy.size;
-                    u32 remaining_input = input_width;
-                    u32 remaining_output = output_width;
-                    while (remaining_size > 0) {
-                        u32 copy_size =
-                            std::min({remaining_input, remaining_output, remaining_size});
-
-                        std::memcpy(dst_pointer, src_pointer, copy_size);
-                        src_pointer += copy_size;
-                        dst_pointer += copy_size;
-
-                        remaining_input -= copy_size;
-                        remaining_output -= copy_size;
-                        remaining_size -= copy_size;
-
-                        if (remaining_input == 0) {
-                            remaining_input = input_width;
-                            src_pointer += input_gap;
-                        }
-                        if (remaining_output == 0) {
-                            remaining_output = output_width;
-                            dst_pointer += output_gap;
-                        }
     }
 
-                    LOG_TRACE(
+    if (config.output_width == 0) {
-                        HW_GPU,
+        LOG_CRITICAL(HW_GPU, "zero output width");
-                        "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> 0x%08X(%u+%u), flags 0x%08X",
+        return;
-                        config.texture_copy.size, config.GetPhysicalInputAddress(), input_width,
-                        input_gap, config.GetPhysicalOutputAddress(), output_width, output_gap,
-                        config.flags);
-
-                    GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PPF);
-                    break;
     }
 
+    if (config.output_height == 0) {
+        LOG_CRITICAL(HW_GPU, "zero output height");
+        return;
+    }
+
+    if (VideoCore::g_renderer->Rasterizer()->AccelerateDisplayTransfer(config))
+        return;
+
+    u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
+    u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
+
     if (config.scaling > config.ScaleXY) {
         LOG_CRITICAL(HW_GPU, "Unimplemented display transfer scaling mode %u",
                      config.scaling.Value());
         UNIMPLEMENTED();
-                    break;
+        return;
     }
 
     if (config.input_linear && config.scaling != config.NoScale) {
         LOG_CRITICAL(HW_GPU, "Scaling is only implemented on tiled input");
         UNIMPLEMENTED();
-                    break;
+        return;
     }
 
     int horizontal_scale = config.scaling != config.NoScale ? 1 : 0;
@@ -247,14 +201,12 @@ inline void Write(u32 addr, const T data) {
     u32 output_width = config.output_width >> horizontal_scale;
     u32 output_height = config.output_height >> vertical_scale;
 
-                u32 input_size = config.input_width * config.input_height *
+    u32 input_size =
-                                 GPU::Regs::BytesPerPixel(config.input_format);
+        config.input_width * config.input_height * GPU::Regs::BytesPerPixel(config.input_format);
-                u32 output_size =
+    u32 output_size = output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
-                    output_width * output_height * GPU::Regs::BytesPerPixel(config.output_format);
 
     Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(), input_size);
-                Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
+    Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(), output_size);
-                                                           output_size);
 
     for (u32 y = 0; y < output_height; ++y) {
         for (u32 x = 0; x < output_width; ++x) {
@@ -265,11 +217,14 @@ inline void Write(u32 addr, const T data) {
             u32 input_x = x << horizontal_scale;
             u32 input_y = y << vertical_scale;
 
+            u32 output_y;
             if (config.flip_vertically) {
                 // Flip the y value of the output data,
                 // we do this after calculating the [x,y] position of the input image
                 // to account for the scaling options.
-                            y = output_height - y - 1;
+                output_y = output_height - y - 1;
+            } else {
+                output_y = y;
             }
 
             u32 dst_bytes_per_pixel = GPU::Regs::BytesPerPixel(config.output_format);
@@ -280,18 +235,16 @@ inline void Write(u32 addr, const T data) {
             if (config.input_linear) {
                 if (!config.dont_swizzle) {
                     // Interpret the input as linear and the output as tiled
-                                u32 coarse_y = y & ~7;
+                    u32 coarse_y = output_y & ~7;
                     u32 stride = output_width * dst_bytes_per_pixel;
 
-                                src_offset =
+                    src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
-                                    (input_x + input_y * config.input_width) * src_bytes_per_pixel;
+                    dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
-                                dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) +
                                  coarse_y * stride;
                 } else {
                     // Both input and output are linear
-                                src_offset =
+                    src_offset = (input_x + input_y * config.input_width) * src_bytes_per_pixel;
-                                    (input_x + input_y * config.input_width) * src_bytes_per_pixel;
+                    dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
-                                dst_offset = (x + y * output_width) * dst_bytes_per_pixel;
                 }
             } else {
                 if (!config.dont_swizzle) {
@@ -299,22 +252,20 @@ inline void Write(u32 addr, const T data) {
                     u32 coarse_y = input_y & ~7;
                     u32 stride = config.input_width * src_bytes_per_pixel;
 
-                                src_offset = VideoCore::GetMortonOffset(input_x, input_y,
+                    src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
-                                                                        src_bytes_per_pixel) +
                                  coarse_y * stride;
-                                dst_offset = (x + y * output_width) * dst_bytes_per_pixel;
+                    dst_offset = (x + output_y * output_width) * dst_bytes_per_pixel;
                 } else {
                     // Both input and output are tiled
-                                u32 out_coarse_y = y & ~7;
+                    u32 out_coarse_y = output_y & ~7;
                     u32 out_stride = output_width * dst_bytes_per_pixel;
 
                     u32 in_coarse_y = input_y & ~7;
                     u32 in_stride = config.input_width * src_bytes_per_pixel;
 
-                                src_offset = VideoCore::GetMortonOffset(input_x, input_y,
+                    src_offset = VideoCore::GetMortonOffset(input_x, input_y, src_bytes_per_pixel) +
-                                                                        src_bytes_per_pixel) +
                                  in_coarse_y * in_stride;
-                                dst_offset = VideoCore::GetMortonOffset(x, y, dst_bytes_per_pixel) +
+                    dst_offset = VideoCore::GetMortonOffset(x, output_y, dst_bytes_per_pixel) +
                                  out_coarse_y * out_stride;
                 }
             }
@@ -326,12 +277,12 @@ inline void Write(u32 addr, const T data) {
                     DecodePixel(config.input_format, src_pixel + src_bytes_per_pixel);
                 src_color = ((src_color + pixel) / 2).Cast<u8>();
             } else if (config.scaling == config.ScaleXY) {
-                            Math::Vec4<u8> pixel1 = DecodePixel(
+                Math::Vec4<u8> pixel1 =
-                                config.input_format, src_pixel + 1 * src_bytes_per_pixel);
+                    DecodePixel(config.input_format, src_pixel + 1 * src_bytes_per_pixel);
-                            Math::Vec4<u8> pixel2 = DecodePixel(
+                Math::Vec4<u8> pixel2 =
-                                config.input_format, src_pixel + 2 * src_bytes_per_pixel);
+                    DecodePixel(config.input_format, src_pixel + 2 * src_bytes_per_pixel);
-                            Math::Vec4<u8> pixel3 = DecodePixel(
+                Math::Vec4<u8> pixel3 =
-                                config.input_format, src_pixel + 3 * src_bytes_per_pixel);
+                    DecodePixel(config.input_format, src_pixel + 3 * src_bytes_per_pixel);
                 src_color = (((src_color + pixel1) + (pixel2 + pixel3)) / 4).Cast<u8>();
             }
 
@@ -364,14 +315,154 @@ inline void Write(u32 addr, const T data) {
             }
         }
     }
+}
 
-                LOG_TRACE(HW_GPU, "DisplayTriggerTransfer: 0x%08x bytes from 0x%08x(%ux%u)-> "
+static void TextureCopy(const Regs::DisplayTransferConfig& config) {
+    const PAddr src_addr = config.GetPhysicalInputAddress();
+    const PAddr dst_addr = config.GetPhysicalOutputAddress();
+
+    // TODO: do hwtest with these cases
+    if (!Memory::IsValidPhysicalAddress(src_addr)) {
+        LOG_CRITICAL(HW_GPU, "invalid input address 0x%08X", src_addr);
+        return;
+    }
+
+    if (!Memory::IsValidPhysicalAddress(dst_addr)) {
+        LOG_CRITICAL(HW_GPU, "invalid output address 0x%08X", dst_addr);
+        return;
+    }
+
+    if (config.texture_copy.input_width == 0) {
+        LOG_CRITICAL(HW_GPU, "zero input width");
+        return;
+    }
+
+    if (config.texture_copy.output_width == 0) {
+        LOG_CRITICAL(HW_GPU, "zero output width");
+        return;
+    }
+
+    if (config.texture_copy.size == 0) {
+        LOG_CRITICAL(HW_GPU, "zero size");
+        return;
+    }
+
+    if (VideoCore::g_renderer->Rasterizer()->AccelerateTextureCopy(config))
+        return;
+
+    u8* src_pointer = Memory::GetPhysicalPointer(src_addr);
+    u8* dst_pointer = Memory::GetPhysicalPointer(dst_addr);
+
+    u32 input_width = config.texture_copy.input_width * 16;
+    u32 input_gap = config.texture_copy.input_gap * 16;
+    u32 output_width = config.texture_copy.output_width * 16;
+    u32 output_gap = config.texture_copy.output_gap * 16;
+
+    size_t contiguous_input_size =
+        config.texture_copy.size / input_width * (input_width + input_gap);
+    Memory::RasterizerFlushRegion(config.GetPhysicalInputAddress(),
+                                  static_cast<u32>(contiguous_input_size));
+
+    size_t contiguous_output_size =
+        config.texture_copy.size / output_width * (output_width + output_gap);
+    Memory::RasterizerFlushAndInvalidateRegion(config.GetPhysicalOutputAddress(),
+                                               static_cast<u32>(contiguous_output_size));
+
+    u32 remaining_size = config.texture_copy.size;
+    u32 remaining_input = input_width;
+    u32 remaining_output = output_width;
+    while (remaining_size > 0) {
+        u32 copy_size = std::min({remaining_input, remaining_output, remaining_size});
+
+        std::memcpy(dst_pointer, src_pointer, copy_size);
+        src_pointer += copy_size;
+        dst_pointer += copy_size;
+
+        remaining_input -= copy_size;
+        remaining_output -= copy_size;
+        remaining_size -= copy_size;
+
+        if (remaining_input == 0) {
+            remaining_input = input_width;
+            src_pointer += input_gap;
+        }
+        if (remaining_output == 0) {
+            remaining_output = output_width;
+            dst_pointer += output_gap;
+        }
+    }
+}
+
+template <typename T>
+inline void Write(u32 addr, const T data) {
+    addr -= HW::VADDR_GPU;
+    u32 index = addr / 4;
+
+    // Writes other than u32 are untested, so I'd rather have them abort than silently fail
+    if (index >= Regs::NumIds() || !std::is_same<T, u32>::value) {
+        LOG_ERROR(HW_GPU, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, addr);
+        return;
+    }
+
+    g_regs[index] = static_cast<u32>(data);
+
+    switch (index) {
+
+    // Memory fills are triggered once the fill value is written.
+    case GPU_REG_INDEX_WORKAROUND(memory_fill_config[0].trigger, 0x00004 + 0x3):
+    case GPU_REG_INDEX_WORKAROUND(memory_fill_config[1].trigger, 0x00008 + 0x3): {
+        const bool is_second_filler = (index != GPU_REG_INDEX(memory_fill_config[0].trigger));
+        auto& config = g_regs.memory_fill_config[is_second_filler];
+
+        if (config.trigger) {
+            MemoryFill(config);
+            LOG_TRACE(HW_GPU, "MemoryFill from 0x%08x to 0x%08x", config.GetStartAddress(),
+                      config.GetEndAddress());
+
+            // It seems that it won't signal interrupt if "address_start" is zero.
+            // TODO: hwtest this
+            if (config.GetStartAddress() != 0) {
+                if (!is_second_filler) {
+                    GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC0);
+                } else {
+                    GSP_GPU::SignalInterrupt(GSP_GPU::InterruptId::PSC1);
+                }
+            }
+
+            // Reset "trigger" flag and set the "finish" flag
+            // NOTE: This was confirmed to happen on hardware even if "address_start" is zero.
+            config.trigger.Assign(0);
+            config.finished.Assign(1);
+        }
+        break;
+    }
+
+    case GPU_REG_INDEX(display_transfer_config.trigger): {
+        MICROPROFILE_SCOPE(GPU_DisplayTransfer);
+
+        const auto& config = g_regs.display_transfer_config;
+        if (config.trigger & 1) {
+
+            if (Pica::g_debug_context)
+                Pica::g_debug_context->OnEvent(Pica::DebugContext::Event::IncomingDisplayTransfer,
+                                               nullptr);
+
+            if (config.is_texture_copy) {
+                TextureCopy(config);
+                LOG_TRACE(HW_GPU, "TextureCopy: 0x%X bytes from 0x%08X(%u+%u)-> "
+                                  "0x%08X(%u+%u), flags 0x%08X",
+                          config.texture_copy.size, config.GetPhysicalInputAddress(),
+                          config.texture_copy.input_width * 16, config.texture_copy.input_gap * 16,
+                          config.GetPhysicalOutputAddress(), config.texture_copy.output_width * 16,
+                          config.texture_copy.output_gap * 16, config.flags);
+            } else {
+                DisplayTransfer(config);
+                LOG_TRACE(HW_GPU, "DisplayTransfer: 0x%08x(%ux%u)-> "
                                   "0x%08x(%ux%u), dst format %x, flags 0x%08X",
-                          config.output_height * output_width *
-                              GPU::Regs::BytesPerPixel(config.output_format),
                           config.GetPhysicalInputAddress(), config.input_width.Value(),
                           config.input_height.Value(), config.GetPhysicalOutputAddress(),
-                          output_width, output_height, config.output_format.Value(), config.flags);
+                          config.output_width.Value(), config.output_height.Value(),
+                          config.output_format.Value(), config.flags);
             }
 
             g_regs.display_transfer_config.trigger = 0;

src/core/memory.cpp

@@ -251,6 +251,9 @@ bool IsValidVirtualAddress(const VAddr vaddr) {
     if (page_pointer)
         return true;
 
+    if (current_page_table->attributes[vaddr >> PAGE_BITS] == PageType::RasterizerCachedMemory)
+        return true;
+
     if (current_page_table->attributes[vaddr >> PAGE_BITS] != PageType::Special)
         return false;
 

src/video_core/rasterizer_interface.h

@@ -42,11 +42,16 @@ public:
     /// and invalidated
     virtual void FlushAndInvalidateRegion(PAddr addr, u32 size) = 0;
 
-    /// Attempt to use a faster method to perform a display transfer
+    /// Attempt to use a faster method to perform a display transfer with is_texture_copy = 0
     virtual bool AccelerateDisplayTransfer(const GPU::Regs::DisplayTransferConfig& config) {
         return false;
     }
 
+    /// Attempt to use a faster method to perform a display transfer with is_texture_copy = 1
+    virtual bool AccelerateTextureCopy(const GPU::Regs::DisplayTransferConfig& config) {
+        return false;
+    }
+
     /// Attempt to use a faster method to fill a region
     virtual bool AccelerateFill(const GPU::Regs::MemoryFillConfig& config) {
         return false;

src/video_core/renderer_opengl/gl_rasterizer.cpp

@@ -709,11 +709,6 @@ bool RasterizerOpenGL::AccelerateDisplayTransfer(const GPU::Regs::DisplayTransfe
     using PixelFormat = CachedSurface::PixelFormat;
     using SurfaceType = CachedSurface::SurfaceType;
 
-    if (config.is_texture_copy) {
-        // TODO(tfarley): Try to hardware accelerate this
-        return false;
-    }
-
     CachedSurface src_params;
     src_params.addr = config.GetPhysicalInputAddress();
     src_params.width = config.output_width;
@@ -768,6 +763,11 @@ bool RasterizerOpenGL::AccelerateDisplayTransfer(const GPU::Regs::DisplayTransfe
     return true;
 }
 
+bool RasterizerOpenGL::AccelerateTextureCopy(const GPU::Regs::DisplayTransferConfig& config) {
+    // TODO(tfarley): Try to hardware accelerate this
+    return false;
+}
+
 bool RasterizerOpenGL::AccelerateFill(const GPU::Regs::MemoryFillConfig& config) {
     using PixelFormat = CachedSurface::PixelFormat;
     using SurfaceType = CachedSurface::SurfaceType;

src/video_core/renderer_opengl/gl_rasterizer.h

@@ -238,6 +238,7 @@ public:
     void FlushRegion(PAddr addr, u32 size) override;
     void FlushAndInvalidateRegion(PAddr addr, u32 size) override;
     bool AccelerateDisplayTransfer(const GPU::Regs::DisplayTransferConfig& config) override;
+    bool AccelerateTextureCopy(const GPU::Regs::DisplayTransferConfig& config) override;
     bool AccelerateFill(const GPU::Regs::MemoryFillConfig& config) override;
     bool AccelerateDisplay(const GPU::Regs::FramebufferConfig& config, PAddr framebuffer_addr,
                            u32 pixel_stride, ScreenInfo& screen_info) override;