Merge pull request #1539 from lioncash/dma
maxwell_dma: Silence compilation warnings
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commit
0f3d8c2574
src/video_core/engines
@ -13,8 +13,7 @@
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#include "video_core/renderer_base.h"
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#include "video_core/renderer_base.h"
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#include "video_core/textures/texture.h"
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#include "video_core/textures/texture.h"
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namespace Tegra {
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namespace Tegra::Engines {
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namespace Engines {
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/// First register id that is actually a Macro call.
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/// First register id that is actually a Macro call.
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constexpr u32 MacroRegistersStart = 0xE00;
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constexpr u32 MacroRegistersStart = 0xE00;
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@ -408,5 +407,4 @@ void Maxwell3D::ProcessClearBuffers() {
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rasterizer.Clear();
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rasterizer.Clear();
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}
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}
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} // namespace Engines
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} // namespace Tegra::Engines
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} // namespace Tegra
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@ -6,8 +6,7 @@
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#include "core/core.h"
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#include "core/core.h"
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#include "video_core/engines/maxwell_compute.h"
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#include "video_core/engines/maxwell_compute.h"
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namespace Tegra {
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namespace Tegra::Engines {
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namespace Engines {
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void MaxwellCompute::WriteReg(u32 method, u32 value) {
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void MaxwellCompute::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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ASSERT_MSG(method < Regs::NUM_REGS,
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@ -26,5 +25,4 @@ void MaxwellCompute::WriteReg(u32 method, u32 value) {
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}
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}
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}
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}
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} // namespace Engines
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} // namespace Tegra::Engines
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} // namespace Tegra
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@ -7,8 +7,7 @@
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#include "video_core/rasterizer_interface.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/textures/decoders.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra {
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namespace Tegra::Engines {
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namespace Engines {
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MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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MaxwellDMA::MaxwellDMA(VideoCore::RasterizerInterface& rasterizer, MemoryManager& memory_manager)
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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: memory_manager(memory_manager), rasterizer{rasterizer} {}
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@ -78,9 +77,9 @@ void MaxwellDMA::HandleCopy() {
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ASSERT(regs.exec.enable_2d == 1);
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ASSERT(regs.exec.enable_2d == 1);
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std::size_t copy_size = regs.x_count * regs.y_count;
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const std::size_t copy_size = regs.x_count * regs.y_count;
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const auto FlushAndInvalidate = [&](u32 src_size, u32 dst_size) {
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const auto FlushAndInvalidate = [&](u32 src_size, u64 dst_size) {
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// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
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// TODO(Subv): For now, manually flush the regions until we implement GPU-accelerated
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// copying.
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// copying.
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rasterizer.FlushRegion(source_cpu, src_size);
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rasterizer.FlushRegion(source_cpu, src_size);
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@ -91,14 +90,11 @@ void MaxwellDMA::HandleCopy() {
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rasterizer.InvalidateRegion(dest_cpu, dst_size);
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rasterizer.InvalidateRegion(dest_cpu, dst_size);
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};
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};
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
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ASSERT(regs.src_params.size_z == 1);
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ASSERT(regs.src_params.size_z == 1);
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
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const u32 src_bytes_per_pixel = regs.src_pitch / regs.src_params.size_x;
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FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y,
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FlushAndInvalidate(regs.src_pitch * regs.src_params.size_y,
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copy_size * src_bytes_per_pixel);
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copy_size * src_bytes_per_pixel);
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@ -111,7 +107,7 @@ void MaxwellDMA::HandleCopy() {
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ASSERT(regs.dst_params.size_z == 1);
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ASSERT(regs.dst_params.size_z == 1);
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ASSERT(regs.src_pitch == regs.x_count);
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ASSERT(regs.src_pitch == regs.x_count);
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u32 src_bpp = regs.src_pitch / regs.x_count;
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const u32 src_bpp = regs.src_pitch / regs.x_count;
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FlushAndInvalidate(regs.src_pitch * regs.y_count,
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FlushAndInvalidate(regs.src_pitch * regs.y_count,
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regs.dst_params.size_x * regs.dst_params.size_y * src_bpp);
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regs.dst_params.size_x * regs.dst_params.size_y * src_bpp);
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@ -122,5 +118,4 @@ void MaxwellDMA::HandleCopy() {
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}
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}
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}
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}
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} // namespace Engines
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} // namespace Tegra::Engines
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} // namespace Tegra
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