2014-04-09 03:15:46 +04:00
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// Copyright 2014 Citra Emulator Project
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2014-12-17 08:38:14 +03:00
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// Licensed under GPLv2 or any later version
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2014-04-09 03:15:46 +04:00
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// Refer to the license.txt file included.
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2013-09-19 07:52:51 +04:00
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2014-04-18 07:05:31 +04:00
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#include <map>
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2015-05-06 10:06:12 +03:00
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#include "common/common_types.h"
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#include "common/logging/log.h"
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#include "common/swap.h"
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2013-09-19 07:52:51 +04:00
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2014-04-09 04:15:08 +04:00
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#include "core/mem_map.h"
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#include "core/hw/hw.h"
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2014-05-07 07:32:04 +04:00
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#include "hle/config_mem.h"
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2015-01-02 08:41:34 +03:00
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#include "hle/shared_page.h"
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2013-09-19 07:52:51 +04:00
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namespace Memory {
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2014-11-18 16:48:11 +03:00
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static std::map<u32, MemoryBlock> heap_map;
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2014-11-23 06:35:45 +03:00
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static std::map<u32, MemoryBlock> heap_linear_map;
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2014-04-18 07:05:31 +04:00
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2015-05-09 09:08:11 +03:00
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PAddr VirtualToPhysicalAddress(const VAddr addr) {
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2015-02-08 16:38:00 +03:00
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if (addr == 0) {
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return 0;
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2015-05-09 09:08:11 +03:00
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} else if (addr >= VRAM_VADDR && addr < VRAM_VADDR_END) {
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return addr - VRAM_VADDR + VRAM_PADDR;
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} else if (addr >= LINEAR_HEAP_VADDR && addr < LINEAR_HEAP_VADDR_END) {
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return addr - LINEAR_HEAP_VADDR + FCRAM_PADDR;
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} else if (addr >= DSP_RAM_VADDR && addr < DSP_RAM_VADDR_END) {
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return addr - DSP_RAM_VADDR + DSP_RAM_PADDR;
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} else if (addr >= IO_AREA_VADDR && addr < IO_AREA_VADDR_END) {
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return addr - IO_AREA_VADDR + IO_AREA_PADDR;
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2014-08-03 03:46:47 +04:00
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}
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2015-05-09 09:08:11 +03:00
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LOG_ERROR(HW_Memory, "Unknown virtual address @ 0x%08x", addr);
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// To help with debugging, set bit on address so that it's obviously invalid.
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return addr | 0x80000000;
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2014-08-03 03:46:47 +04:00
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}
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2014-04-26 22:21:40 +04:00
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2015-05-09 09:08:11 +03:00
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VAddr PhysicalToVirtualAddress(const PAddr addr) {
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2015-02-08 16:38:00 +03:00
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if (addr == 0) {
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return 0;
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2015-05-09 09:08:11 +03:00
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} else if (addr >= VRAM_PADDR && addr < VRAM_PADDR_END) {
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return addr - VRAM_PADDR + VRAM_VADDR;
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} else if (addr >= FCRAM_PADDR && addr < FCRAM_PADDR_END) {
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return addr - FCRAM_PADDR + LINEAR_HEAP_VADDR;
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} else if (addr >= DSP_RAM_PADDR && addr < DSP_RAM_PADDR_END) {
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return addr - DSP_RAM_PADDR + DSP_RAM_VADDR;
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} else if (addr >= IO_AREA_PADDR && addr < IO_AREA_PADDR_END) {
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return addr - IO_AREA_PADDR + IO_AREA_VADDR;
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2014-04-18 02:40:42 +04:00
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}
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2014-08-03 03:46:47 +04:00
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2015-05-09 09:08:11 +03:00
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LOG_ERROR(HW_Memory, "Unknown physical address @ 0x%08x", addr);
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// To help with debugging, set bit on address so that it's obviously invalid.
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return addr | 0x80000000;
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2014-04-18 02:40:42 +04:00
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}
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2013-09-19 07:52:51 +04:00
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template <typename T>
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2014-08-28 22:20:55 +04:00
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inline void Read(T &var, const VAddr vaddr) {
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2014-04-02 02:18:02 +04:00
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// TODO: Figure out the fastest order of tests for both read and write (they are probably different).
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// TODO: Make sure this represents the mirrors in a correct way.
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// Could just do a base-relative read, too.... TODO
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2013-09-19 07:52:51 +04:00
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2014-05-08 05:04:55 +04:00
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// Kernel memory command buffer
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2015-05-09 06:39:56 +03:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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var = *((const T*)&g_tls_mem[vaddr - TLS_AREA_VADDR]);
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2014-04-13 05:55:36 +04:00
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2014-04-30 07:16:12 +04:00
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// ExeFS:/.code is loaded here
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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var = *((const T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR]);
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2014-04-30 07:16:12 +04:00
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2014-11-23 06:35:45 +03:00
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// FCRAM - linear heap
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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var = *((const T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR]);
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2014-04-18 05:15:40 +04:00
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2014-04-18 05:05:34 +04:00
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// FCRAM - application heap
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2014-04-25 07:56:06 +04:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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var = *((const T*)&g_heap[vaddr - HEAP_VADDR]);
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2014-04-18 02:40:42 +04:00
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2014-04-25 07:56:06 +04:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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var = *((const T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR]);
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2014-04-25 07:56:06 +04:00
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2014-05-07 07:32:04 +04:00
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// Config memory
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} else if ((vaddr >= CONFIG_MEMORY_VADDR) && (vaddr < CONFIG_MEMORY_VADDR_END)) {
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ConfigMem::Read<T>(var, vaddr);
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2015-01-02 08:41:34 +03:00
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// Shared page
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} else if ((vaddr >= SHARED_PAGE_VADDR) && (vaddr < SHARED_PAGE_VADDR_END)) {
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SharedPage::Read<T>(var, vaddr);
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2014-12-30 06:35:06 +03:00
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// DSP memory
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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var = *((const T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR]);
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2014-12-30 06:35:06 +03:00
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2014-04-26 09:27:25 +04:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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var = *((const T*)&g_vram[vaddr - VRAM_VADDR]);
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2014-04-26 09:27:25 +04:00
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2014-04-04 06:04:50 +04:00
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} else {
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2014-12-06 04:53:49 +03:00
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LOG_ERROR(HW_Memory, "unknown Read%lu @ 0x%08X", sizeof(var) * 8, vaddr);
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2014-04-02 02:18:02 +04:00
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}
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2013-09-19 07:52:51 +04:00
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}
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template <typename T>
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2014-08-28 22:20:55 +04:00
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inline void Write(const VAddr vaddr, const T data) {
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2014-08-03 03:46:47 +04:00
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2014-05-08 05:04:55 +04:00
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// Kernel memory command buffer
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2015-05-09 06:39:56 +03:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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*(T*)&g_tls_mem[vaddr - TLS_AREA_VADDR] = data;
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2014-04-13 05:55:36 +04:00
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2014-04-30 07:16:12 +04:00
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// ExeFS:/.code is loaded here
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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*(T*)&g_exefs_code[vaddr - PROCESS_IMAGE_VADDR] = data;
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2014-04-30 07:16:12 +04:00
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2014-11-23 06:35:45 +03:00
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// FCRAM - linear heap
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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*(T*)&g_heap_linear[vaddr - LINEAR_HEAP_VADDR] = data;
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2014-04-18 05:05:34 +04:00
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// FCRAM - application heap
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2014-04-25 07:56:06 +04:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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*(T*)&g_heap[vaddr - HEAP_VADDR] = data;
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2014-04-04 06:04:50 +04:00
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2014-04-25 07:56:06 +04:00
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// Shared memory
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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*(T*)&g_shared_mem[vaddr - SHARED_MEMORY_VADDR] = data;
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2014-04-25 07:56:06 +04:00
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2014-04-26 09:27:25 +04:00
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// VRAM
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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*(T*)&g_vram[vaddr - VRAM_VADDR] = data;
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2014-04-26 09:27:25 +04:00
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2014-12-30 06:35:06 +03:00
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// DSP memory
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= DSP_RAM_VADDR) && (vaddr < DSP_RAM_VADDR_END)) {
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*(T*)&g_dsp_mem[vaddr - DSP_RAM_VADDR] = data;
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2014-12-30 06:35:06 +03:00
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2014-05-07 07:32:04 +04:00
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//} else if ((vaddr & 0xFFFF0000) == 0x1FF80000) {
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2015-01-21 04:16:47 +03:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to Configuration Memory");
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2014-05-07 07:32:04 +04:00
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//} else if ((vaddr & 0xFFFFF000) == 0x1FF81000) {
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2015-01-21 04:16:47 +03:00
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// ASSERT_MSG(MEMMAP, false, "umimplemented write to shared page");
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2014-08-03 03:46:47 +04:00
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2014-04-04 06:04:50 +04:00
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// Error out...
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2014-04-02 02:18:02 +04:00
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} else {
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2014-12-06 04:53:49 +03:00
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LOG_ERROR(HW_Memory, "unknown Write%lu 0x%08X @ 0x%08X", sizeof(data) * 8, (u32)data, vaddr);
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2014-04-02 02:18:02 +04:00
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}
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2013-09-19 07:52:51 +04:00
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}
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2014-08-28 22:20:55 +04:00
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u8 *GetPointer(const VAddr vaddr) {
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2014-05-08 05:04:55 +04:00
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// Kernel memory command buffer
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2015-05-09 06:39:56 +03:00
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if (vaddr >= TLS_AREA_VADDR && vaddr < TLS_AREA_VADDR_END) {
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return g_tls_mem + (vaddr - TLS_AREA_VADDR);
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2014-05-08 05:04:55 +04:00
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2014-04-30 07:16:12 +04:00
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// ExeFS:/.code is loaded here
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= PROCESS_IMAGE_VADDR) && (vaddr < PROCESS_IMAGE_VADDR_END)) {
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return g_exefs_code + (vaddr - PROCESS_IMAGE_VADDR);
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2014-04-30 07:16:12 +04:00
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2014-11-23 06:35:45 +03:00
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// FCRAM - linear heap
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2015-05-09 06:39:56 +03:00
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} else if ((vaddr >= LINEAR_HEAP_VADDR) && (vaddr < LINEAR_HEAP_VADDR_END)) {
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return g_heap_linear + (vaddr - LINEAR_HEAP_VADDR);
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2014-04-18 05:15:40 +04:00
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2014-04-18 05:05:34 +04:00
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// FCRAM - application heap
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2014-04-18 05:40:42 +04:00
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} else if ((vaddr >= HEAP_VADDR) && (vaddr < HEAP_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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return g_heap + (vaddr - HEAP_VADDR);
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2014-04-18 02:40:42 +04:00
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2014-04-25 07:56:06 +04:00
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// Shared memory
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2014-05-16 02:56:28 +04:00
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} else if ((vaddr >= SHARED_MEMORY_VADDR) && (vaddr < SHARED_MEMORY_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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return g_shared_mem + (vaddr - SHARED_MEMORY_VADDR);
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2014-04-25 07:56:06 +04:00
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2014-04-26 09:27:25 +04:00
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// VRAM
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2014-07-23 06:38:21 +04:00
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} else if ((vaddr >= VRAM_VADDR) && (vaddr < VRAM_VADDR_END)) {
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2014-12-03 09:13:29 +03:00
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return g_vram + (vaddr - VRAM_VADDR);
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2014-04-26 09:27:25 +04:00
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2014-04-07 06:56:08 +04:00
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} else {
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2014-12-06 04:53:49 +03:00
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LOG_ERROR(HW_Memory, "unknown GetPointer @ 0x%08x", vaddr);
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2014-04-02 02:18:02 +04:00
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return 0;
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}
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2014-03-25 18:50:34 +04:00
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}
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2014-04-25 06:32:26 +04:00
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u32 MapBlock_Heap(u32 size, u32 operation, u32 permissions) {
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MemoryBlock block;
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2014-08-03 03:46:47 +04:00
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2014-04-25 06:32:26 +04:00
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block.base_address = HEAP_VADDR;
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block.size = size;
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block.operation = operation;
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block.permissions = permissions;
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2014-08-03 03:46:47 +04:00
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2014-11-18 16:48:11 +03:00
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if (heap_map.size() > 0) {
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const MemoryBlock last_block = heap_map.rbegin()->second;
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2014-04-25 06:32:26 +04:00
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block.address = last_block.address + last_block.size;
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}
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2014-11-18 16:48:11 +03:00
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heap_map[block.GetVirtualAddress()] = block;
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2014-04-25 06:32:26 +04:00
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return block.GetVirtualAddress();
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}
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2014-11-23 06:35:45 +03:00
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u32 MapBlock_HeapLinear(u32 size, u32 operation, u32 permissions) {
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2014-04-25 06:32:26 +04:00
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MemoryBlock block;
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2014-08-03 03:46:47 +04:00
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2015-05-09 06:39:56 +03:00
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block.base_address = LINEAR_HEAP_VADDR;
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2014-04-18 07:05:31 +04:00
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block.size = size;
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block.operation = operation;
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block.permissions = permissions;
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2014-08-03 03:46:47 +04:00
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2014-11-23 06:35:45 +03:00
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if (heap_linear_map.size() > 0) {
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const MemoryBlock last_block = heap_linear_map.rbegin()->second;
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2014-04-18 07:05:31 +04:00
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block.address = last_block.address + last_block.size;
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}
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2014-11-23 06:35:45 +03:00
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heap_linear_map[block.GetVirtualAddress()] = block;
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2014-04-18 07:05:31 +04:00
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return block.GetVirtualAddress();
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}
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2015-04-28 04:59:06 +03:00
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void MemBlock_Init() {
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}
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void MemBlock_Shutdown() {
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heap_map.clear();
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heap_linear_map.clear();
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}
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2014-08-28 22:20:55 +04:00
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u8 Read8(const VAddr addr) {
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2014-07-25 03:46:10 +04:00
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u8 data = 0;
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Read<u8>(data, addr);
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2014-08-28 22:20:55 +04:00
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return data;
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2013-09-19 07:52:51 +04:00
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}
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2014-08-28 22:20:55 +04:00
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u16 Read16(const VAddr addr) {
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2014-07-25 03:46:10 +04:00
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u16_le data = 0;
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Read<u16_le>(data, addr);
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2015-05-13 00:17:04 +03:00
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return data;
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2013-09-19 07:52:51 +04:00
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}
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2014-08-28 22:20:55 +04:00
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u32 Read32(const VAddr addr) {
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2014-07-25 03:46:10 +04:00
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u32_le data = 0;
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Read<u32_le>(data, addr);
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2015-05-13 00:17:04 +03:00
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return data;
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2013-09-19 07:52:51 +04:00
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}
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2015-03-11 23:10:14 +03:00
|
|
|
u64 Read64(const VAddr addr) {
|
|
|
|
u64_le data = 0;
|
|
|
|
Read<u64_le>(data, addr);
|
2015-05-13 00:17:04 +03:00
|
|
|
return data;
|
2013-09-19 07:52:51 +04:00
|
|
|
}
|
|
|
|
|
2014-08-28 22:20:55 +04:00
|
|
|
void Write8(const VAddr addr, const u8 data) {
|
2014-07-05 07:46:16 +04:00
|
|
|
Write<u8>(addr, data);
|
2013-09-19 07:52:51 +04:00
|
|
|
}
|
|
|
|
|
2014-08-28 22:20:55 +04:00
|
|
|
void Write16(const VAddr addr, const u16 data) {
|
2014-07-05 07:46:16 +04:00
|
|
|
Write<u16_le>(addr, data);
|
2013-09-19 07:52:51 +04:00
|
|
|
}
|
|
|
|
|
2014-08-28 22:20:55 +04:00
|
|
|
void Write32(const VAddr addr, const u32 data) {
|
2014-07-05 07:46:16 +04:00
|
|
|
Write<u32_le>(addr, data);
|
2013-09-19 07:52:51 +04:00
|
|
|
}
|
|
|
|
|
2014-08-28 22:20:55 +04:00
|
|
|
void Write64(const VAddr addr, const u64 data) {
|
2014-07-05 07:46:16 +04:00
|
|
|
Write<u64_le>(addr, data);
|
2013-09-19 07:52:51 +04:00
|
|
|
}
|
|
|
|
|
2014-08-28 22:20:55 +04:00
|
|
|
void WriteBlock(const VAddr addr, const u8* data, const size_t size) {
|
2014-09-28 19:30:29 +04:00
|
|
|
u32 offset = 0;
|
2014-08-17 22:23:54 +04:00
|
|
|
while (offset < (size & ~3)) {
|
|
|
|
Write32(addr + offset, *(u32*)&data[offset]);
|
|
|
|
offset += 4;
|
|
|
|
}
|
2014-06-25 02:51:31 +04:00
|
|
|
|
2014-08-17 22:23:54 +04:00
|
|
|
if (size & 2) {
|
|
|
|
Write16(addr + offset, *(u16*)&data[offset]);
|
|
|
|
offset += 2;
|
|
|
|
}
|
2014-06-25 02:51:31 +04:00
|
|
|
|
|
|
|
if (size & 1)
|
|
|
|
Write8(addr + offset, data[offset]);
|
|
|
|
}
|
|
|
|
|
2013-09-19 07:52:51 +04:00
|
|
|
} // namespace
|