2020-05-29 07:53:27 +03:00
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// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <memory>
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#include <unordered_map>
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#include <vector>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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namespace Tegra {
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2020-06-04 18:42:19 +03:00
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2020-05-29 07:53:27 +03:00
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namespace Engines {
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class Maxwell3D;
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}
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2020-06-04 18:42:19 +03:00
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2020-05-29 07:53:27 +03:00
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namespace Macro {
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constexpr std::size_t NUM_MACRO_REGISTERS = 8;
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enum class Operation : u32 {
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ALU = 0,
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AddImmediate = 1,
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ExtractInsert = 2,
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ExtractShiftLeftImmediate = 3,
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ExtractShiftLeftRegister = 4,
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Read = 5,
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Unused = 6, // This operation doesn't seem to be a valid encoding.
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Branch = 7,
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};
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enum class ALUOperation : u32 {
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Add = 0,
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AddWithCarry = 1,
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Subtract = 2,
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SubtractWithBorrow = 3,
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// Operations 4-7 don't seem to be valid encodings.
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Xor = 8,
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Or = 9,
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And = 10,
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AndNot = 11,
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Nand = 12
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};
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enum class ResultOperation : u32 {
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IgnoreAndFetch = 0,
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Move = 1,
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MoveAndSetMethod = 2,
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FetchAndSend = 3,
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MoveAndSend = 4,
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FetchAndSetMethod = 5,
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MoveAndSetMethodFetchAndSend = 6,
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MoveAndSetMethodSend = 7
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};
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enum class BranchCondition : u32 {
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Zero = 0,
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NotZero = 1,
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};
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union Opcode {
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u32 raw;
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BitField<0, 3, Operation> operation;
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BitField<4, 3, ResultOperation> result_operation;
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BitField<4, 1, BranchCondition> branch_condition;
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// If set on a branch, then the branch doesn't have a delay slot.
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BitField<5, 1, u32> branch_annul;
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BitField<7, 1, u32> is_exit;
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BitField<8, 3, u32> dst;
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BitField<11, 3, u32> src_a;
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BitField<14, 3, u32> src_b;
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// The signed immediate overlaps the second source operand and the alu operation.
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BitField<14, 18, s32> immediate;
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BitField<17, 5, ALUOperation> alu_operation;
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// Bitfield instructions data
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BitField<17, 5, u32> bf_src_bit;
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BitField<22, 5, u32> bf_size;
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BitField<27, 5, u32> bf_dst_bit;
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u32 GetBitfieldMask() const {
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return (1 << bf_size) - 1;
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}
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s32 GetBranchTarget() const {
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return static_cast<s32>(immediate * sizeof(u32));
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}
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};
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union MethodAddress {
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u32 raw;
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BitField<0, 12, u32> address;
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BitField<12, 6, u32> increment;
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};
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} // namespace Macro
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2020-06-04 18:42:19 +03:00
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class HLEMacro;
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2020-05-29 07:53:27 +03:00
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class CachedMacro {
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public:
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virtual ~CachedMacro() = default;
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/**
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* Executes the macro code with the specified input parameters.
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* @param code The macro byte code to execute
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* @param parameters The parameters of the macro
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*/
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2020-06-03 09:33:38 +03:00
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virtual void Execute(const std::vector<u32>& parameters, u32 method) = 0;
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2020-05-29 07:53:27 +03:00
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};
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class MacroEngine {
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public:
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2020-06-04 18:42:19 +03:00
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MacroEngine(Engines::Maxwell3D& maxwell3d);
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virtual ~MacroEngine();
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2020-05-29 07:53:27 +03:00
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// Store the uploaded macro code to compile them when they're called.
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void AddCode(u32 method, u32 data);
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// Compiles the macro if its not in the cache, and executes the compiled macro
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2020-06-04 18:42:19 +03:00
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void Execute(Engines::Maxwell3D& maxwell3d, u32 method, const std::vector<u32>& parameters);
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2020-05-29 07:53:27 +03:00
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protected:
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virtual std::unique_ptr<CachedMacro> Compile(const std::vector<u32>& code) = 0;
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private:
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2020-06-04 18:42:19 +03:00
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struct CacheInfo {
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std::unique_ptr<CachedMacro> lle_program{};
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std::unique_ptr<CachedMacro> hle_program{};
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u64 hash{};
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bool has_hle_program{};
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};
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std::unordered_map<u32, CacheInfo> macro_cache;
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2020-05-29 07:53:27 +03:00
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std::unordered_map<u32, std::vector<u32>> uploaded_macro_code;
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std::unique_ptr<HLEMacro> hle_macros;
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2020-05-29 07:53:27 +03:00
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};
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std::unique_ptr<MacroEngine> GetMacroEngine(Engines::Maxwell3D& maxwell3d);
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} // namespace Tegra
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