2018-03-18 23:15:05 +03:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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2021-10-01 07:57:02 +03:00
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#include <array>
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#include <atomic>
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2020-02-25 05:04:12 +03:00
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#include <chrono>
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2021-10-01 07:57:02 +03:00
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#include <condition_variable>
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#include <list>
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#include <memory>
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2020-02-25 05:04:12 +03:00
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2018-08-11 01:39:37 +03:00
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#include "common/assert.h"
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2019-09-26 02:43:23 +03:00
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#include "common/microprofile.h"
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2021-04-15 02:07:40 +03:00
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#include "common/settings.h"
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2019-02-14 20:42:58 +03:00
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#include "core/core.h"
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2019-01-30 05:49:18 +03:00
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#include "core/core_timing.h"
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2020-03-25 05:58:49 +03:00
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#include "core/frontend/emu_window.h"
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2020-12-12 09:26:14 +03:00
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#include "core/hardware_interrupt_manager.h"
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2021-10-01 07:57:02 +03:00
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "core/hle/service/nvflinger/buffer_queue.h"
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2021-05-16 03:34:20 +03:00
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#include "core/perf_stats.h"
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2021-10-01 07:57:02 +03:00
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#include "video_core/cdma_pusher.h"
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#include "video_core/dma_pusher.h"
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2018-03-18 23:15:05 +03:00
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#include "video_core/engines/fermi_2d.h"
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2019-01-23 02:49:31 +03:00
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#include "video_core/engines/kepler_compute.h"
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2018-09-08 23:58:20 +03:00
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#include "video_core/engines/kepler_memory.h"
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2018-03-18 23:15:05 +03:00
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#include "video_core/engines/maxwell_3d.h"
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2018-06-11 01:02:33 +03:00
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#include "video_core/engines/maxwell_dma.h"
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2018-03-18 23:15:05 +03:00
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#include "video_core/gpu.h"
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2021-10-01 07:57:02 +03:00
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#include "video_core/gpu_thread.h"
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2019-03-04 07:54:16 +03:00
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#include "video_core/memory_manager.h"
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2019-01-08 07:32:02 +03:00
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#include "video_core/renderer_base.h"
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2020-07-10 06:36:38 +03:00
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#include "video_core/shader_notify.h"
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2018-03-18 23:15:05 +03:00
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namespace Tegra {
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2019-09-26 02:43:23 +03:00
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MICROPROFILE_DEFINE(GPU_wait, "GPU", "Wait for the GPU", MP_RGB(128, 128, 192));
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2021-10-01 07:57:02 +03:00
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struct GPU::Impl {
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explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
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: gpu{gpu_}, system{system_}, memory_manager{std::make_unique<Tegra::MemoryManager>(
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system)},
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dma_pusher{std::make_unique<Tegra::DmaPusher>(system, gpu)}, use_nvdec{use_nvdec_},
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maxwell_3d{std::make_unique<Engines::Maxwell3D>(system, *memory_manager)},
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fermi_2d{std::make_unique<Engines::Fermi2D>()},
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kepler_compute{std::make_unique<Engines::KeplerCompute>(system, *memory_manager)},
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maxwell_dma{std::make_unique<Engines::MaxwellDMA>(system, *memory_manager)},
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kepler_memory{std::make_unique<Engines::KeplerMemory>(system, *memory_manager)},
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shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
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gpu_thread{system_, is_async_} {}
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~Impl() = default;
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
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renderer = std::move(renderer_);
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rasterizer = renderer->ReadRasterizer();
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memory_manager->BindRasterizer(rasterizer);
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maxwell_3d->BindRasterizer(rasterizer);
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fermi_2d->BindRasterizer(rasterizer);
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kepler_compute->BindRasterizer(rasterizer);
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maxwell_dma->BindRasterizer(rasterizer);
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}
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/// Calls a GPU method.
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void CallMethod(const GPU::MethodCall& method_call) {
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LOG_TRACE(HW_GPU, "Processing method {:08X} on subchannel {}", method_call.method,
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method_call.subchannel);
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ASSERT(method_call.subchannel < bound_engines.size());
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if (ExecuteMethodOnEngine(method_call.method)) {
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CallEngineMethod(method_call);
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} else {
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CallPullerMethod(method_call);
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}
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}
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/// Calls a GPU multivalue method.
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void CallMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
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u32 methods_pending) {
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LOG_TRACE(HW_GPU, "Processing method {:08X} on subchannel {}", method, subchannel);
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ASSERT(subchannel < bound_engines.size());
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if (ExecuteMethodOnEngine(method)) {
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CallEngineMultiMethod(method, subchannel, base_start, amount, methods_pending);
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} else {
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for (std::size_t i = 0; i < amount; i++) {
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CallPullerMethod(GPU::MethodCall{
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method,
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base_start[i],
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subchannel,
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methods_pending - static_cast<u32>(i),
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});
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}
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}
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}
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands() {
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rasterizer->FlushCommands();
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}
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/// Synchronizes CPU writes with Host GPU memory.
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void SyncGuestHost() {
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rasterizer->SyncGuestHost();
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}
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/// Signal the ending of command list.
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void OnCommandListEnd() {
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if (is_async) {
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// This command only applies to asynchronous GPU mode
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gpu_thread.OnCommandListEnd();
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}
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}
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/// Request a host GPU memory flush from the CPU.
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[[nodiscard]] u64 RequestFlush(VAddr addr, std::size_t size) {
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std::unique_lock lck{flush_request_mutex};
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const u64 fence = ++last_flush_fence;
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flush_requests.emplace_back(fence, addr, size);
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return fence;
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}
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentFlushRequestFence() const {
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return current_flush_fence.load(std::memory_order_relaxed);
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}
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/// Tick pending requests within the GPU.
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void TickWork() {
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std::unique_lock lck{flush_request_mutex};
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while (!flush_requests.empty()) {
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auto& request = flush_requests.front();
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const u64 fence = request.fence;
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const VAddr addr = request.addr;
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const std::size_t size = request.size;
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flush_requests.pop_front();
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flush_request_mutex.unlock();
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rasterizer->FlushRegion(addr, size);
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current_flush_fence.store(fence);
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flush_request_mutex.lock();
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}
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}
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/// Returns a reference to the Maxwell3D GPU engine.
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[[nodiscard]] Engines::Maxwell3D& Maxwell3D() {
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return *maxwell_3d;
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}
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/// Returns a const reference to the Maxwell3D GPU engine.
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[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const {
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return *maxwell_3d;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] Engines::KeplerCompute& KeplerCompute() {
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return *kepler_compute;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const {
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return *kepler_compute;
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}
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/// Returns a reference to the GPU memory manager.
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[[nodiscard]] Tegra::MemoryManager& MemoryManager() {
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return *memory_manager;
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}
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/// Returns a const reference to the GPU memory manager.
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[[nodiscard]] const Tegra::MemoryManager& MemoryManager() const {
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return *memory_manager;
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}
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher() {
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return *dma_pusher;
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}
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/// Returns a const reference to the GPU DMA pusher.
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[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const {
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return *dma_pusher;
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}
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/// Returns a reference to the underlying renderer.
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[[nodiscard]] VideoCore::RendererBase& Renderer() {
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return *renderer;
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}
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/// Returns a const reference to the underlying renderer.
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const {
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return *renderer;
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}
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/// Returns a reference to the shader notifier.
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() {
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return *shader_notify;
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}
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const {
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return *shader_notify;
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}
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/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame.
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void WaitFence(u32 syncpoint_id, u32 value) {
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// Synced GPU, is always in sync
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if (!is_async) {
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return;
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}
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if (syncpoint_id == UINT32_MAX) {
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// TODO: Research what this does.
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LOG_ERROR(HW_GPU, "Waiting for syncpoint -1 not implemented");
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return;
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}
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MICROPROFILE_SCOPE(GPU_wait);
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std::unique_lock lock{sync_mutex};
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sync_cv.wait(lock, [=, this] {
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if (shutting_down.load(std::memory_order_relaxed)) {
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// We're shutting down, ensure no threads continue to wait for the next syncpoint
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return true;
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}
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return syncpoints.at(syncpoint_id).load() >= value;
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});
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}
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void IncrementSyncPoint(u32 syncpoint_id) {
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auto& syncpoint = syncpoints.at(syncpoint_id);
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syncpoint++;
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std::lock_guard lock{sync_mutex};
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sync_cv.notify_all();
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auto& interrupt = syncpt_interrupts.at(syncpoint_id);
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if (!interrupt.empty()) {
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u32 value = syncpoint.load();
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auto it = interrupt.begin();
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while (it != interrupt.end()) {
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if (value >= *it) {
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TriggerCpuInterrupt(syncpoint_id, *it);
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it = interrupt.erase(it);
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continue;
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}
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it++;
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}
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}
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}
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[[nodiscard]] u32 GetSyncpointValue(u32 syncpoint_id) const {
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return syncpoints.at(syncpoint_id).load();
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}
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void RegisterSyncptInterrupt(u32 syncpoint_id, u32 value) {
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2021-10-02 06:10:55 +03:00
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std::lock_guard lock{sync_mutex};
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2021-10-01 07:57:02 +03:00
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auto& interrupt = syncpt_interrupts.at(syncpoint_id);
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bool contains = std::any_of(interrupt.begin(), interrupt.end(),
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[value](u32 in_value) { return in_value == value; });
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if (contains) {
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return;
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}
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interrupt.emplace_back(value);
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}
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[[nodiscard]] bool CancelSyncptInterrupt(u32 syncpoint_id, u32 value) {
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std::lock_guard lock{sync_mutex};
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auto& interrupt = syncpt_interrupts.at(syncpoint_id);
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const auto iter =
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std::find_if(interrupt.begin(), interrupt.end(),
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[value](u32 interrupt_value) { return value == interrupt_value; });
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if (iter == interrupt.end()) {
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return false;
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}
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interrupt.erase(iter);
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return true;
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}
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[[nodiscard]] u64 GetTicks() const {
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// This values were reversed engineered by fincs from NVN
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// The gpu clock is reported in units of 385/625 nanoseconds
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constexpr u64 gpu_ticks_num = 384;
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constexpr u64 gpu_ticks_den = 625;
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u64 nanoseconds = system.CoreTiming().GetGlobalTimeNs().count();
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if (Settings::values.use_fast_gpu_time.GetValue()) {
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nanoseconds /= 256;
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}
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const u64 nanoseconds_num = nanoseconds / gpu_ticks_den;
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const u64 nanoseconds_rem = nanoseconds % gpu_ticks_den;
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return nanoseconds_num * gpu_ticks_num + (nanoseconds_rem * gpu_ticks_num) / gpu_ticks_den;
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}
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[[nodiscard]] bool IsAsync() const {
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return is_async;
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}
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[[nodiscard]] bool UseNvdec() const {
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return use_nvdec;
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}
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void RendererFrameEndNotify() {
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system.GetPerfStats().EndGameFrame();
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}
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start() {
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gpu_thread.StartThread(*renderer, renderer->Context(), *dma_pusher);
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cpu_context = renderer->GetRenderWindow().CreateSharedContext();
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cpu_context->MakeCurrent();
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}
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/// Obtain the CPU Context
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void ObtainContext() {
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cpu_context->MakeCurrent();
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}
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/// Release the CPU Context
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void ReleaseContext() {
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cpu_context->DoneCurrent();
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}
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/// Push GPU command entries to be processed
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void PushGPUEntries(Tegra::CommandList&& entries) {
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gpu_thread.SubmitList(std::move(entries));
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}
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/// Push GPU command buffer entries to be processed
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2021-12-02 07:19:43 +03:00
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void PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
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2021-10-01 07:57:02 +03:00
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if (!use_nvdec) {
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return;
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}
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2021-12-02 07:19:43 +03:00
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if (cdma_pushers.find(id) == cdma_pushers.end()) {
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cdma_pushers[id] = std::make_unique<Tegra::CDmaPusher>(gpu);
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2021-10-01 07:57:02 +03:00
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}
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|
|
// SubmitCommandBuffer would make the nvdec operations async, this is not currently working
|
|
|
|
// TODO(ameerj): RE proper async nvdec operation
|
|
|
|
// gpu_thread.SubmitCommandBuffer(std::move(entries));
|
2021-12-02 07:19:43 +03:00
|
|
|
cdma_pushers[id]->ProcessEntries(std::move(entries));
|
2021-10-01 07:57:02 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Frees the CDMAPusher instance to free up resources
|
2021-12-02 07:19:43 +03:00
|
|
|
void ClearCdmaInstance(u32 id) {
|
|
|
|
if (cdma_pushers.find(id) != cdma_pushers.end()) {
|
|
|
|
cdma_pushers.erase(id);
|
|
|
|
}
|
2021-10-01 07:57:02 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Swap buffers (render frame)
|
|
|
|
void SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
|
|
|
gpu_thread.SwapBuffers(framebuffer);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
|
|
|
|
void FlushRegion(VAddr addr, u64 size) {
|
|
|
|
gpu_thread.FlushRegion(addr, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Notify rasterizer that any caches of the specified region should be invalidated
|
|
|
|
void InvalidateRegion(VAddr addr, u64 size) {
|
|
|
|
gpu_thread.InvalidateRegion(addr, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
|
|
|
|
void FlushAndInvalidateRegion(VAddr addr, u64 size) {
|
|
|
|
gpu_thread.FlushAndInvalidateRegion(addr, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const {
|
|
|
|
auto& interrupt_manager = system.InterruptManager();
|
|
|
|
interrupt_manager.GPUInterruptSyncpt(syncpoint_id, value);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessBindMethod(const GPU::MethodCall& method_call) {
|
|
|
|
// Bind the current subchannel to the desired engine id.
|
|
|
|
LOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", method_call.subchannel,
|
|
|
|
method_call.argument);
|
|
|
|
const auto engine_id = static_cast<EngineID>(method_call.argument);
|
|
|
|
bound_engines[method_call.subchannel] = static_cast<EngineID>(engine_id);
|
|
|
|
switch (engine_id) {
|
|
|
|
case EngineID::FERMI_TWOD_A:
|
|
|
|
dma_pusher->BindSubchannel(fermi_2d.get(), method_call.subchannel);
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_B:
|
|
|
|
dma_pusher->BindSubchannel(maxwell_3d.get(), method_call.subchannel);
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_COMPUTE_B:
|
|
|
|
dma_pusher->BindSubchannel(kepler_compute.get(), method_call.subchannel);
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_DMA_COPY_A:
|
|
|
|
dma_pusher->BindSubchannel(maxwell_dma.get(), method_call.subchannel);
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_INLINE_TO_MEMORY_B:
|
|
|
|
dma_pusher->BindSubchannel(kepler_memory.get(), method_call.subchannel);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented engine {:04X}", engine_id);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessFenceActionMethod() {
|
|
|
|
switch (regs.fence_action.op) {
|
|
|
|
case GPU::FenceOperation::Acquire:
|
|
|
|
WaitFence(regs.fence_action.syncpoint_id, regs.fence_value);
|
|
|
|
break;
|
|
|
|
case GPU::FenceOperation::Increment:
|
|
|
|
IncrementSyncPoint(regs.fence_action.syncpoint_id);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented operation {}", regs.fence_action.op.Value());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessWaitForInterruptMethod() {
|
|
|
|
// TODO(bunnei) ImplementMe
|
|
|
|
LOG_WARNING(HW_GPU, "(STUBBED) called");
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessSemaphoreTriggerMethod() {
|
|
|
|
const auto semaphoreOperationMask = 0xF;
|
|
|
|
const auto op =
|
|
|
|
static_cast<GpuSemaphoreOperation>(regs.semaphore_trigger & semaphoreOperationMask);
|
|
|
|
if (op == GpuSemaphoreOperation::WriteLong) {
|
|
|
|
struct Block {
|
|
|
|
u32 sequence;
|
|
|
|
u32 zeros = 0;
|
|
|
|
u64 timestamp;
|
|
|
|
};
|
|
|
|
|
|
|
|
Block block{};
|
|
|
|
block.sequence = regs.semaphore_sequence;
|
|
|
|
// TODO(Kmather73): Generate a real GPU timestamp and write it here instead of
|
|
|
|
// CoreTiming
|
|
|
|
block.timestamp = GetTicks();
|
|
|
|
memory_manager->WriteBlock(regs.semaphore_address.SemaphoreAddress(), &block,
|
|
|
|
sizeof(block));
|
|
|
|
} else {
|
|
|
|
const u32 word{memory_manager->Read<u32>(regs.semaphore_address.SemaphoreAddress())};
|
|
|
|
if ((op == GpuSemaphoreOperation::AcquireEqual && word == regs.semaphore_sequence) ||
|
|
|
|
(op == GpuSemaphoreOperation::AcquireGequal &&
|
|
|
|
static_cast<s32>(word - regs.semaphore_sequence) > 0) ||
|
|
|
|
(op == GpuSemaphoreOperation::AcquireMask && (word & regs.semaphore_sequence))) {
|
|
|
|
// Nothing to do in this case
|
|
|
|
} else {
|
|
|
|
regs.acquire_source = true;
|
|
|
|
regs.acquire_value = regs.semaphore_sequence;
|
|
|
|
if (op == GpuSemaphoreOperation::AcquireEqual) {
|
|
|
|
regs.acquire_active = true;
|
|
|
|
regs.acquire_mode = false;
|
|
|
|
} else if (op == GpuSemaphoreOperation::AcquireGequal) {
|
|
|
|
regs.acquire_active = true;
|
|
|
|
regs.acquire_mode = true;
|
|
|
|
} else if (op == GpuSemaphoreOperation::AcquireMask) {
|
|
|
|
// TODO(kemathe) The acquire mask operation waits for a value that, ANDed with
|
|
|
|
// semaphore_sequence, gives a non-0 result
|
|
|
|
LOG_ERROR(HW_GPU, "Invalid semaphore operation AcquireMask not implemented");
|
|
|
|
} else {
|
|
|
|
LOG_ERROR(HW_GPU, "Invalid semaphore operation");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessSemaphoreRelease() {
|
|
|
|
memory_manager->Write<u32>(regs.semaphore_address.SemaphoreAddress(),
|
|
|
|
regs.semaphore_release);
|
|
|
|
}
|
|
|
|
|
|
|
|
void ProcessSemaphoreAcquire() {
|
|
|
|
const u32 word = memory_manager->Read<u32>(regs.semaphore_address.SemaphoreAddress());
|
|
|
|
const auto value = regs.semaphore_acquire;
|
|
|
|
if (word != value) {
|
|
|
|
regs.acquire_active = true;
|
|
|
|
regs.acquire_value = value;
|
|
|
|
// TODO(kemathe73) figure out how to do the acquire_timeout
|
|
|
|
regs.acquire_mode = false;
|
|
|
|
regs.acquire_source = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Calls a GPU puller method.
|
|
|
|
void CallPullerMethod(const GPU::MethodCall& method_call) {
|
|
|
|
regs.reg_array[method_call.method] = method_call.argument;
|
|
|
|
const auto method = static_cast<BufferMethods>(method_call.method);
|
|
|
|
|
|
|
|
switch (method) {
|
|
|
|
case BufferMethods::BindObject: {
|
|
|
|
ProcessBindMethod(method_call);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::Nop:
|
|
|
|
case BufferMethods::SemaphoreAddressHigh:
|
|
|
|
case BufferMethods::SemaphoreAddressLow:
|
|
|
|
case BufferMethods::SemaphoreSequence:
|
|
|
|
case BufferMethods::UnkCacheFlush:
|
|
|
|
case BufferMethods::WrcacheFlush:
|
|
|
|
case BufferMethods::FenceValue:
|
|
|
|
break;
|
|
|
|
case BufferMethods::RefCnt:
|
|
|
|
rasterizer->SignalReference();
|
|
|
|
break;
|
|
|
|
case BufferMethods::FenceAction:
|
|
|
|
ProcessFenceActionMethod();
|
|
|
|
break;
|
|
|
|
case BufferMethods::WaitForInterrupt:
|
|
|
|
ProcessWaitForInterruptMethod();
|
|
|
|
break;
|
|
|
|
case BufferMethods::SemaphoreTrigger: {
|
|
|
|
ProcessSemaphoreTriggerMethod();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::NotifyIntr: {
|
|
|
|
// TODO(Kmather73): Research and implement this method.
|
|
|
|
LOG_ERROR(HW_GPU, "Special puller engine method NotifyIntr not implemented");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::Unk28: {
|
|
|
|
// TODO(Kmather73): Research and implement this method.
|
|
|
|
LOG_ERROR(HW_GPU, "Special puller engine method Unk28 not implemented");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::SemaphoreAcquire: {
|
|
|
|
ProcessSemaphoreAcquire();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::SemaphoreRelease: {
|
|
|
|
ProcessSemaphoreRelease();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case BufferMethods::Yield: {
|
|
|
|
// TODO(Kmather73): Research and implement this method.
|
|
|
|
LOG_ERROR(HW_GPU, "Special puller engine method Yield not implemented");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
LOG_ERROR(HW_GPU, "Special puller engine method {:X} not implemented", method);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Calls a GPU engine method.
|
|
|
|
void CallEngineMethod(const GPU::MethodCall& method_call) {
|
|
|
|
const EngineID engine = bound_engines[method_call.subchannel];
|
|
|
|
|
|
|
|
switch (engine) {
|
|
|
|
case EngineID::FERMI_TWOD_A:
|
|
|
|
fermi_2d->CallMethod(method_call.method, method_call.argument,
|
|
|
|
method_call.IsLastCall());
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_B:
|
|
|
|
maxwell_3d->CallMethod(method_call.method, method_call.argument,
|
|
|
|
method_call.IsLastCall());
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_COMPUTE_B:
|
|
|
|
kepler_compute->CallMethod(method_call.method, method_call.argument,
|
|
|
|
method_call.IsLastCall());
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_DMA_COPY_A:
|
|
|
|
maxwell_dma->CallMethod(method_call.method, method_call.argument,
|
|
|
|
method_call.IsLastCall());
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_INLINE_TO_MEMORY_B:
|
|
|
|
kepler_memory->CallMethod(method_call.method, method_call.argument,
|
|
|
|
method_call.IsLastCall());
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented engine");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Calls a GPU engine multivalue method.
|
|
|
|
void CallEngineMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
|
|
|
|
u32 methods_pending) {
|
|
|
|
const EngineID engine = bound_engines[subchannel];
|
|
|
|
|
|
|
|
switch (engine) {
|
|
|
|
case EngineID::FERMI_TWOD_A:
|
|
|
|
fermi_2d->CallMultiMethod(method, base_start, amount, methods_pending);
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_B:
|
|
|
|
maxwell_3d->CallMultiMethod(method, base_start, amount, methods_pending);
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_COMPUTE_B:
|
|
|
|
kepler_compute->CallMultiMethod(method, base_start, amount, methods_pending);
|
|
|
|
break;
|
|
|
|
case EngineID::MAXWELL_DMA_COPY_A:
|
|
|
|
maxwell_dma->CallMultiMethod(method, base_start, amount, methods_pending);
|
|
|
|
break;
|
|
|
|
case EngineID::KEPLER_INLINE_TO_MEMORY_B:
|
|
|
|
kepler_memory->CallMultiMethod(method, base_start, amount, methods_pending);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
UNIMPLEMENTED_MSG("Unimplemented engine");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Determines where the method should be executed.
|
|
|
|
[[nodiscard]] bool ExecuteMethodOnEngine(u32 method) {
|
|
|
|
const auto buffer_method = static_cast<BufferMethods>(method);
|
|
|
|
return buffer_method >= BufferMethods::NonPullerMethods;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct Regs {
|
|
|
|
static constexpr size_t NUM_REGS = 0x40;
|
|
|
|
|
|
|
|
union {
|
|
|
|
struct {
|
|
|
|
INSERT_PADDING_WORDS_NOINIT(0x4);
|
|
|
|
struct {
|
|
|
|
u32 address_high;
|
|
|
|
u32 address_low;
|
|
|
|
|
|
|
|
[[nodiscard]] GPUVAddr SemaphoreAddress() const {
|
|
|
|
return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
|
|
|
|
address_low);
|
|
|
|
}
|
|
|
|
} semaphore_address;
|
|
|
|
|
|
|
|
u32 semaphore_sequence;
|
|
|
|
u32 semaphore_trigger;
|
|
|
|
INSERT_PADDING_WORDS_NOINIT(0xC);
|
|
|
|
|
|
|
|
// The pusher and the puller share the reference counter, the pusher only has read
|
|
|
|
// access
|
|
|
|
u32 reference_count;
|
|
|
|
INSERT_PADDING_WORDS_NOINIT(0x5);
|
|
|
|
|
|
|
|
u32 semaphore_acquire;
|
|
|
|
u32 semaphore_release;
|
|
|
|
u32 fence_value;
|
|
|
|
GPU::FenceAction fence_action;
|
|
|
|
INSERT_PADDING_WORDS_NOINIT(0xE2);
|
|
|
|
|
|
|
|
// Puller state
|
|
|
|
u32 acquire_mode;
|
|
|
|
u32 acquire_source;
|
|
|
|
u32 acquire_active;
|
|
|
|
u32 acquire_timeout;
|
|
|
|
u32 acquire_value;
|
|
|
|
};
|
|
|
|
std::array<u32, NUM_REGS> reg_array;
|
|
|
|
};
|
|
|
|
} regs{};
|
|
|
|
|
|
|
|
GPU& gpu;
|
|
|
|
Core::System& system;
|
|
|
|
std::unique_ptr<Tegra::MemoryManager> memory_manager;
|
|
|
|
std::unique_ptr<Tegra::DmaPusher> dma_pusher;
|
2021-12-02 07:19:43 +03:00
|
|
|
std::map<u32, std::unique_ptr<Tegra::CDmaPusher>> cdma_pushers;
|
2021-10-01 07:57:02 +03:00
|
|
|
std::unique_ptr<VideoCore::RendererBase> renderer;
|
|
|
|
VideoCore::RasterizerInterface* rasterizer = nullptr;
|
|
|
|
const bool use_nvdec;
|
|
|
|
|
|
|
|
/// Mapping of command subchannels to their bound engine ids
|
|
|
|
std::array<EngineID, 8> bound_engines{};
|
|
|
|
/// 3D engine
|
|
|
|
std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
|
|
|
|
/// 2D engine
|
|
|
|
std::unique_ptr<Engines::Fermi2D> fermi_2d;
|
|
|
|
/// Compute engine
|
|
|
|
std::unique_ptr<Engines::KeplerCompute> kepler_compute;
|
|
|
|
/// DMA engine
|
|
|
|
std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
|
|
|
|
/// Inline memory engine
|
|
|
|
std::unique_ptr<Engines::KeplerMemory> kepler_memory;
|
|
|
|
/// Shader build notifier
|
|
|
|
std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
|
|
|
|
/// When true, we are about to shut down emulation session, so terminate outstanding tasks
|
|
|
|
std::atomic_bool shutting_down{};
|
|
|
|
|
|
|
|
std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
|
|
|
|
|
|
|
|
std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
|
|
|
|
|
|
|
|
std::mutex sync_mutex;
|
|
|
|
std::mutex device_mutex;
|
|
|
|
|
|
|
|
std::condition_variable sync_cv;
|
|
|
|
|
|
|
|
struct FlushRequest {
|
|
|
|
explicit FlushRequest(u64 fence_, VAddr addr_, std::size_t size_)
|
|
|
|
: fence{fence_}, addr{addr_}, size{size_} {}
|
|
|
|
u64 fence;
|
|
|
|
VAddr addr;
|
|
|
|
std::size_t size;
|
|
|
|
};
|
|
|
|
|
|
|
|
std::list<FlushRequest> flush_requests;
|
|
|
|
std::atomic<u64> current_flush_fence{};
|
|
|
|
u64 last_flush_fence{};
|
|
|
|
std::mutex flush_request_mutex;
|
|
|
|
|
|
|
|
const bool is_async;
|
|
|
|
|
|
|
|
VideoCommon::GPUThread::ThreadManager gpu_thread;
|
|
|
|
std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context;
|
|
|
|
|
|
|
|
#define ASSERT_REG_POSITION(field_name, position) \
|
|
|
|
static_assert(offsetof(Regs, field_name) == position * 4, \
|
|
|
|
"Field " #field_name " has invalid position")
|
|
|
|
|
|
|
|
ASSERT_REG_POSITION(semaphore_address, 0x4);
|
|
|
|
ASSERT_REG_POSITION(semaphore_sequence, 0x6);
|
|
|
|
ASSERT_REG_POSITION(semaphore_trigger, 0x7);
|
|
|
|
ASSERT_REG_POSITION(reference_count, 0x14);
|
|
|
|
ASSERT_REG_POSITION(semaphore_acquire, 0x1A);
|
|
|
|
ASSERT_REG_POSITION(semaphore_release, 0x1B);
|
|
|
|
ASSERT_REG_POSITION(fence_value, 0x1C);
|
|
|
|
ASSERT_REG_POSITION(fence_action, 0x1D);
|
|
|
|
|
|
|
|
ASSERT_REG_POSITION(acquire_mode, 0x100);
|
|
|
|
ASSERT_REG_POSITION(acquire_source, 0x101);
|
|
|
|
ASSERT_REG_POSITION(acquire_active, 0x102);
|
|
|
|
ASSERT_REG_POSITION(acquire_timeout, 0x103);
|
|
|
|
ASSERT_REG_POSITION(acquire_value, 0x104);
|
|
|
|
|
|
|
|
#undef ASSERT_REG_POSITION
|
|
|
|
|
|
|
|
enum class GpuSemaphoreOperation {
|
|
|
|
AcquireEqual = 0x1,
|
|
|
|
WriteLong = 0x2,
|
|
|
|
AcquireGequal = 0x4,
|
|
|
|
AcquireMask = 0x8,
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
|
|
|
|
: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
|
2018-03-18 23:15:05 +03:00
|
|
|
|
|
|
|
GPU::~GPU() = default;
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer) {
|
|
|
|
impl->BindRenderer(std::move(renderer));
|
|
|
|
}
|
2020-06-11 06:58:57 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::CallMethod(const MethodCall& method_call) {
|
|
|
|
impl->CallMethod(method_call);
|
2020-06-11 06:58:57 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::CallMultiMethod(u32 method, u32 subchannel, const u32* base_start, u32 amount,
|
|
|
|
u32 methods_pending) {
|
|
|
|
impl->CallMultiMethod(method, subchannel, base_start, amount, methods_pending);
|
2018-07-21 01:31:36 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::FlushCommands() {
|
|
|
|
impl->FlushCommands();
|
2018-03-22 23:19:35 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::SyncGuestHost() {
|
|
|
|
impl->SyncGuestHost();
|
2019-07-15 04:25:13 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::OnCommandListEnd() {
|
|
|
|
impl->OnCommandListEnd();
|
2019-07-15 04:25:13 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
u64 GPU::RequestFlush(VAddr addr, std::size_t size) {
|
|
|
|
return impl->RequestFlush(addr, size);
|
2018-08-28 17:57:56 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
u64 GPU::CurrentFlushRequestFence() const {
|
|
|
|
return impl->CurrentFlushRequestFence();
|
2018-08-28 17:57:56 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::TickWork() {
|
|
|
|
impl->TickWork();
|
2018-11-24 07:20:56 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
Engines::Maxwell3D& GPU::Maxwell3D() {
|
|
|
|
return impl->Maxwell3D();
|
2020-10-27 06:07:36 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const Engines::Maxwell3D& GPU::Maxwell3D() const {
|
|
|
|
return impl->Maxwell3D();
|
2018-11-24 07:20:56 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
Engines::KeplerCompute& GPU::KeplerCompute() {
|
|
|
|
return impl->KeplerCompute();
|
2020-10-27 06:07:36 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const Engines::KeplerCompute& GPU::KeplerCompute() const {
|
|
|
|
return impl->KeplerCompute();
|
2019-06-07 19:56:30 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
Tegra::MemoryManager& GPU::MemoryManager() {
|
|
|
|
return impl->MemoryManager();
|
2019-06-07 19:56:30 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const Tegra::MemoryManager& GPU::MemoryManager() const {
|
|
|
|
return impl->MemoryManager();
|
2019-06-07 19:56:30 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
Tegra::DmaPusher& GPU::DmaPusher() {
|
|
|
|
return impl->DmaPusher();
|
|
|
|
}
|
2019-06-19 03:53:21 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const Tegra::DmaPusher& GPU::DmaPusher() const {
|
|
|
|
return impl->DmaPusher();
|
2019-06-08 04:13:20 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
VideoCore::RendererBase& GPU::Renderer() {
|
|
|
|
return impl->Renderer();
|
|
|
|
}
|
2020-02-14 01:16:07 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const VideoCore::RendererBase& GPU::Renderer() const {
|
|
|
|
return impl->Renderer();
|
2020-02-10 17:32:51 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
VideoCore::ShaderNotify& GPU::ShaderNotify() {
|
|
|
|
return impl->ShaderNotify();
|
2021-05-16 03:34:20 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
|
|
|
|
return impl->ShaderNotify();
|
2019-07-26 21:20:43 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::WaitFence(u32 syncpoint_id, u32 value) {
|
|
|
|
impl->WaitFence(syncpoint_id, value);
|
2020-02-16 16:51:37 +03:00
|
|
|
}
|
2020-02-16 23:24:37 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::IncrementSyncPoint(u32 syncpoint_id) {
|
|
|
|
impl->IncrementSyncPoint(syncpoint_id);
|
|
|
|
}
|
2018-11-24 07:20:56 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
u32 GPU::GetSyncpointValue(u32 syncpoint_id) const {
|
|
|
|
return impl->GetSyncpointValue(syncpoint_id);
|
|
|
|
}
|
2018-11-24 07:20:56 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::RegisterSyncptInterrupt(u32 syncpoint_id, u32 value) {
|
|
|
|
impl->RegisterSyncptInterrupt(syncpoint_id, value);
|
|
|
|
}
|
2018-11-24 07:20:56 +03:00
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
bool GPU::CancelSyncptInterrupt(u32 syncpoint_id, u32 value) {
|
|
|
|
return impl->CancelSyncptInterrupt(syncpoint_id, value);
|
2019-01-30 05:49:18 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
u64 GPU::GetTicks() const {
|
|
|
|
return impl->GetTicks();
|
2020-04-20 09:16:56 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
bool GPU::IsAsync() const {
|
|
|
|
return impl->IsAsync();
|
2019-01-30 05:49:18 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
bool GPU::UseNvdec() const {
|
|
|
|
return impl->UseNvdec();
|
2019-01-30 05:49:18 +03:00
|
|
|
}
|
|
|
|
|
2021-10-01 07:57:02 +03:00
|
|
|
void GPU::RendererFrameEndNotify() {
|
|
|
|
impl->RendererFrameEndNotify();
|
2019-01-30 05:49:18 +03:00
|
|
|
}
|
|
|
|
|
2020-12-12 09:26:14 +03:00
|
|
|
void GPU::Start() {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->Start();
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::ObtainContext() {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->ObtainContext();
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::ReleaseContext() {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->ReleaseContext();
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::PushGPUEntries(Tegra::CommandList&& entries) {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->PushGPUEntries(std::move(entries));
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
2021-12-02 07:19:43 +03:00
|
|
|
void GPU::PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
|
|
|
|
impl->PushCommandBuffer(id, entries);
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
2021-12-02 07:19:43 +03:00
|
|
|
void GPU::ClearCdmaInstance(u32 id) {
|
|
|
|
impl->ClearCdmaInstance(id);
|
2021-03-30 12:37:40 +03:00
|
|
|
}
|
|
|
|
|
2020-12-12 09:26:14 +03:00
|
|
|
void GPU::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->SwapBuffers(framebuffer);
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::FlushRegion(VAddr addr, u64 size) {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->FlushRegion(addr, size);
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::InvalidateRegion(VAddr addr, u64 size) {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->InvalidateRegion(addr, size);
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::FlushAndInvalidateRegion(VAddr addr, u64 size) {
|
2021-10-01 07:57:02 +03:00
|
|
|
impl->FlushAndInvalidateRegion(addr, size);
|
2020-12-12 09:26:14 +03:00
|
|
|
}
|
|
|
|
|
2018-03-18 23:15:05 +03:00
|
|
|
} // namespace Tegra
|