2019-03-02 23:20:28 +03:00
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// Copyright 2019 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.
Configure Dynarmic to mask out these bits on pointer reads.
While we are at it, remove some unused attributes carried over from
Citra.
Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:
mov rdi,rcx
shr rdx,0Ch
mov r8,qword ptr [rax+8]
mov rax,qword ptr [r8+rdx*8]
mov rdx,rax
-and al,3
and rdx,0FFFFFFFFFFFFFFFCh
je Core::Memory::Memory::Impl::Read<unsigned char>
mov rax,qword ptr [vaddr]
movzx eax,byte ptr [rdx+rax]
2020-12-30 03:16:57 +03:00
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#include <atomic>
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2020-11-18 03:58:41 +03:00
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#include <tuple>
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2019-03-02 23:20:28 +03:00
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#include "common/common_types.h"
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2020-04-09 05:49:51 +03:00
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#include "common/virtual_buffer.h"
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2019-03-02 23:20:28 +03:00
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namespace Common {
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enum class PageType : u8 {
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/// Page is unmapped and should cause an access error.
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Unmapped,
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/// Page is mapped to regular memory. This is the only type you can get pointers to.
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Memory,
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/// Page is mapped to regular memory, but also needs to check for rasterizer cache flushing and
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/// invalidation
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RasterizerCachedMemory,
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};
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/**
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* A (reasonably) fast way of allowing switchable and remappable process address spaces. It loosely
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* mimics the way a real CPU page table works.
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*/
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struct PageTable {
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2022-02-19 10:42:27 +03:00
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struct TraversalEntry {
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u64 phys_addr{};
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std::size_t block_size{};
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};
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struct TraversalContext {
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u64 next_page{};
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u64 next_offset{};
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};
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core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.
Configure Dynarmic to mask out these bits on pointer reads.
While we are at it, remove some unused attributes carried over from
Citra.
Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:
mov rdi,rcx
shr rdx,0Ch
mov r8,qword ptr [rax+8]
mov rax,qword ptr [r8+rdx*8]
mov rdx,rax
-and al,3
and rdx,0FFFFFFFFFFFFFFFCh
je Core::Memory::Memory::Impl::Read<unsigned char>
mov rax,qword ptr [vaddr]
movzx eax,byte ptr [rdx+rax]
2020-12-30 03:16:57 +03:00
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/// Number of bits reserved for attribute tagging.
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/// This can be at most the guaranteed alignment of the pointers in the page table.
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static constexpr int ATTRIBUTE_BITS = 2;
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/**
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* Pair of host pointer and page type attribute.
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* This uses the lower bits of a given pointer to store the attribute tag.
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* Writing and reading the pointer attribute pair is guaranteed to be atomic for the same method
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* call. In other words, they are guaranteed to be synchronized at all times.
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*/
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class PageInfo {
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public:
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/// Returns the page pointer
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[[nodiscard]] u8* Pointer() const noexcept {
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return ExtractPointer(raw.load(std::memory_order_relaxed));
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}
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/// Returns the page type attribute
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[[nodiscard]] PageType Type() const noexcept {
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return ExtractType(raw.load(std::memory_order_relaxed));
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}
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/// Returns the page pointer and attribute pair, extracted from the same atomic read
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[[nodiscard]] std::pair<u8*, PageType> PointerType() const noexcept {
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const uintptr_t non_atomic_raw = raw.load(std::memory_order_relaxed);
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return {ExtractPointer(non_atomic_raw), ExtractType(non_atomic_raw)};
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}
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/// Returns the raw representation of the page information.
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/// Use ExtractPointer and ExtractType to unpack the value.
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[[nodiscard]] uintptr_t Raw() const noexcept {
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return raw.load(std::memory_order_relaxed);
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}
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/// Write a page pointer and type pair atomically
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void Store(u8* pointer, PageType type) noexcept {
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raw.store(reinterpret_cast<uintptr_t>(pointer) | static_cast<uintptr_t>(type));
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}
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/// Unpack a pointer from a page info raw representation
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[[nodiscard]] static u8* ExtractPointer(uintptr_t raw) noexcept {
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return reinterpret_cast<u8*>(raw & (~uintptr_t{0} << ATTRIBUTE_BITS));
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}
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/// Unpack a page type from a page info raw representation
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[[nodiscard]] static PageType ExtractType(uintptr_t raw) noexcept {
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return static_cast<PageType>(raw & ((uintptr_t{1} << ATTRIBUTE_BITS) - 1));
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}
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private:
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std::atomic<uintptr_t> raw;
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};
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2020-04-09 05:49:51 +03:00
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PageTable();
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2020-11-18 03:58:41 +03:00
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~PageTable() noexcept;
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PageTable(const PageTable&) = delete;
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PageTable& operator=(const PageTable&) = delete;
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PageTable(PageTable&&) noexcept = default;
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PageTable& operator=(PageTable&&) noexcept = default;
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2019-03-02 23:20:28 +03:00
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2022-02-19 10:42:27 +03:00
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bool BeginTraversal(TraversalEntry* out_entry, TraversalContext* out_context,
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u64 address) const;
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bool ContinueTraversal(TraversalEntry* out_entry, TraversalContext* context) const;
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2019-03-02 23:20:28 +03:00
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/**
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2021-01-02 17:00:05 +03:00
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* Resizes the page table to be able to accommodate enough pages within
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2019-03-02 23:20:28 +03:00
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* a given address space.
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*
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* @param address_space_width_in_bits The address size width in bits.
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2020-11-18 03:45:17 +03:00
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* @param page_size_in_bits The page size in bits.
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2019-03-02 23:20:28 +03:00
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*/
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2022-02-19 10:42:27 +03:00
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void Resize(std::size_t address_space_width_in_bits, std::size_t page_size_in_bits);
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2019-03-02 23:20:28 +03:00
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2022-02-19 10:42:27 +03:00
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std::size_t GetAddressSpaceBits() const {
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2021-05-29 10:24:09 +03:00
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return current_address_space_width_in_bits;
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}
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2019-03-02 23:20:28 +03:00
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/**
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* Vector of memory pointers backing each page. An entry can only be non-null if the
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core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.
Configure Dynarmic to mask out these bits on pointer reads.
While we are at it, remove some unused attributes carried over from
Citra.
Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:
mov rdi,rcx
shr rdx,0Ch
mov r8,qword ptr [rax+8]
mov rax,qword ptr [r8+rdx*8]
mov rdx,rax
-and al,3
and rdx,0FFFFFFFFFFFFFFFCh
je Core::Memory::Memory::Impl::Read<unsigned char>
mov rax,qword ptr [vaddr]
movzx eax,byte ptr [rdx+rax]
2020-12-30 03:16:57 +03:00
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* corresponding attribute element is of type `Memory`.
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2019-03-02 23:20:28 +03:00
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*/
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core/memory: Read and write page table atomically
Squash attributes into the pointer's integer, making them an uintptr_t
pair containing 2 bits at the bottom and then the pointer. These bits
are currently unused thanks to alignment requirements.
Configure Dynarmic to mask out these bits on pointer reads.
While we are at it, remove some unused attributes carried over from
Citra.
Read/Write and other hot functions use a two step unpacking process that
is less readable to stop MSVC from emitting an extra AND instruction in
the hot path:
mov rdi,rcx
shr rdx,0Ch
mov r8,qword ptr [rax+8]
mov rax,qword ptr [r8+rdx*8]
mov rdx,rax
-and al,3
and rdx,0FFFFFFFFFFFFFFFCh
je Core::Memory::Memory::Impl::Read<unsigned char>
mov rax,qword ptr [vaddr]
movzx eax,byte ptr [rdx+rax]
2020-12-30 03:16:57 +03:00
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VirtualBuffer<PageInfo> pointers;
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2020-03-13 23:33:47 +03:00
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2020-04-09 05:49:51 +03:00
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VirtualBuffer<u64> backing_addr;
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2021-05-29 10:24:09 +03:00
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2022-02-19 10:42:27 +03:00
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std::size_t current_address_space_width_in_bits{};
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u8* fastmem_arena{};
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2020-01-19 03:49:30 +03:00
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2022-02-19 10:42:27 +03:00
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std::size_t page_size{};
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2020-03-13 23:33:47 +03:00
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};
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2019-03-02 23:20:28 +03:00
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} // namespace Common
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