2015-05-13 04:38:29 +03:00
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// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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2016-11-24 22:42:32 +03:00
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#include <array>
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2015-06-21 15:12:49 +03:00
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#include <cstddef>
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2016-06-27 20:42:42 +03:00
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#include <string>
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2015-05-13 04:38:29 +03:00
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#include "common/common_types.h"
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namespace Memory {
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2015-05-13 05:38:56 +03:00
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/**
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* Page size used by the ARM architecture. This is the smallest granularity with which memory can
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* be mapped.
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*/
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2015-05-13 04:38:29 +03:00
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const u32 PAGE_SIZE = 0x1000;
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2015-07-19 08:22:28 +03:00
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const u32 PAGE_MASK = PAGE_SIZE - 1;
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const int PAGE_BITS = 12;
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2016-11-24 22:42:32 +03:00
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const size_t PAGE_TABLE_NUM_ENTRIES = 1 << (32 - PAGE_BITS);
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2015-05-13 04:38:29 +03:00
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/// Physical memory regions as seen from the ARM11
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enum : PAddr {
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/// IO register area
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2016-09-18 03:38:01 +03:00
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IO_AREA_PADDR = 0x10100000,
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IO_AREA_SIZE = 0x01000000, ///< IO area size (16MB)
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2015-05-13 04:38:29 +03:00
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IO_AREA_PADDR_END = IO_AREA_PADDR + IO_AREA_SIZE,
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/// MPCore internal memory region
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MPCORE_RAM_PADDR = 0x17E00000,
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MPCORE_RAM_SIZE = 0x00002000, ///< MPCore internal memory size (8KB)
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2015-05-13 04:38:29 +03:00
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MPCORE_RAM_PADDR_END = MPCORE_RAM_PADDR + MPCORE_RAM_SIZE,
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/// Video memory
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VRAM_PADDR = 0x18000000,
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VRAM_SIZE = 0x00600000, ///< VRAM size (6MB)
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VRAM_PADDR_END = VRAM_PADDR + VRAM_SIZE,
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/// DSP memory
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DSP_RAM_PADDR = 0x1FF00000,
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DSP_RAM_SIZE = 0x00080000, ///< DSP memory size (512KB)
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DSP_RAM_PADDR_END = DSP_RAM_PADDR + DSP_RAM_SIZE,
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/// AXI WRAM
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AXI_WRAM_PADDR = 0x1FF80000,
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AXI_WRAM_SIZE = 0x00080000, ///< AXI WRAM size (512KB)
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AXI_WRAM_PADDR_END = AXI_WRAM_PADDR + AXI_WRAM_SIZE,
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/// Main FCRAM
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FCRAM_PADDR = 0x20000000,
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FCRAM_SIZE = 0x08000000, ///< FCRAM size (128MB)
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FCRAM_PADDR_END = FCRAM_PADDR + FCRAM_SIZE,
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};
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/// Virtual user-space memory regions
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enum : VAddr {
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/// Where the application text, data and bss reside.
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PROCESS_IMAGE_VADDR = 0x00100000,
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PROCESS_IMAGE_MAX_SIZE = 0x03F00000,
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PROCESS_IMAGE_VADDR_END = PROCESS_IMAGE_VADDR + PROCESS_IMAGE_MAX_SIZE,
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/// Area where IPC buffers are mapped onto.
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IPC_MAPPING_VADDR = 0x04000000,
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IPC_MAPPING_SIZE = 0x04000000,
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IPC_MAPPING_VADDR_END = IPC_MAPPING_VADDR + IPC_MAPPING_SIZE,
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/// Application heap (includes stack).
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HEAP_VADDR = 0x08000000,
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HEAP_SIZE = 0x08000000,
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HEAP_VADDR_END = HEAP_VADDR + HEAP_SIZE,
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/// Area where shared memory buffers are mapped onto.
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SHARED_MEMORY_VADDR = 0x10000000,
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SHARED_MEMORY_SIZE = 0x04000000,
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SHARED_MEMORY_VADDR_END = SHARED_MEMORY_VADDR + SHARED_MEMORY_SIZE,
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/// Maps 1:1 to an offset in FCRAM. Used for HW allocations that need to be linear in physical
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/// memory.
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LINEAR_HEAP_VADDR = 0x14000000,
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LINEAR_HEAP_SIZE = 0x08000000,
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LINEAR_HEAP_VADDR_END = LINEAR_HEAP_VADDR + LINEAR_HEAP_SIZE,
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/// Maps 1:1 to the IO register area.
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IO_AREA_VADDR = 0x1EC00000,
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IO_AREA_VADDR_END = IO_AREA_VADDR + IO_AREA_SIZE,
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/// Maps 1:1 to VRAM.
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VRAM_VADDR = 0x1F000000,
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VRAM_VADDR_END = VRAM_VADDR + VRAM_SIZE,
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/// Maps 1:1 to DSP memory.
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DSP_RAM_VADDR = 0x1FF00000,
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DSP_RAM_VADDR_END = DSP_RAM_VADDR + DSP_RAM_SIZE,
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/// Read-only page containing kernel and system configuration values.
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CONFIG_MEMORY_VADDR = 0x1FF80000,
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CONFIG_MEMORY_SIZE = 0x00001000,
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CONFIG_MEMORY_VADDR_END = CONFIG_MEMORY_VADDR + CONFIG_MEMORY_SIZE,
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/// Usually read-only page containing mostly values read from hardware.
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SHARED_PAGE_VADDR = 0x1FF81000,
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SHARED_PAGE_SIZE = 0x00001000,
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SHARED_PAGE_VADDR_END = SHARED_PAGE_VADDR + SHARED_PAGE_SIZE,
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/// Area where TLS (Thread-Local Storage) buffers are allocated.
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TLS_AREA_VADDR = 0x1FF82000,
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TLS_ENTRY_SIZE = 0x200,
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2015-08-06 03:39:53 +03:00
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2015-08-06 03:26:52 +03:00
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/// Equivalent to LINEAR_HEAP_VADDR, but expanded to cover the extra memory in the New 3DS.
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NEW_LINEAR_HEAP_VADDR = 0x30000000,
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NEW_LINEAR_HEAP_SIZE = 0x10000000,
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NEW_LINEAR_HEAP_VADDR_END = NEW_LINEAR_HEAP_VADDR + NEW_LINEAR_HEAP_SIZE,
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};
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2016-04-16 10:46:11 +03:00
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bool IsValidVirtualAddress(const VAddr addr);
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bool IsValidPhysicalAddress(const PAddr addr);
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u8 Read8(VAddr addr);
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u16 Read16(VAddr addr);
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u32 Read32(VAddr addr);
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u64 Read64(VAddr addr);
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void Write8(VAddr addr, u8 data);
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void Write16(VAddr addr, u16 data);
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void Write32(VAddr addr, u32 data);
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void Write64(VAddr addr, u64 data);
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2016-04-19 22:08:02 +03:00
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void ReadBlock(const VAddr src_addr, void* dest_buffer, size_t size);
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void WriteBlock(const VAddr dest_addr, const void* src_buffer, size_t size);
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void ZeroBlock(const VAddr dest_addr, const size_t size);
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void CopyBlock(VAddr dest_addr, VAddr src_addr, size_t size);
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u8* GetPointer(VAddr virtual_address);
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2016-06-27 20:42:42 +03:00
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std::string ReadCString(VAddr virtual_address, std::size_t max_length);
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2015-07-29 17:54:44 +03:00
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/**
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* Converts a virtual address inside a region with 1:1 mapping to physical memory to a physical
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* address. This should be used by services to translate addresses for use by the hardware.
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*/
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PAddr VirtualToPhysicalAddress(VAddr addr);
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/**
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* Undoes a mapping performed by VirtualToPhysicalAddress().
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*/
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VAddr PhysicalToVirtualAddress(PAddr addr);
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2015-05-13 04:38:29 +03:00
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/**
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* Gets a pointer to the memory region beginning at the specified physical address.
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*
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* @note This is currently implemented using PhysicalToVirtualAddress().
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*/
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u8* GetPhysicalPointer(PAddr address);
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2016-04-17 01:57:57 +03:00
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/**
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* Adds the supplied value to the rasterizer resource cache counter of each
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* page touching the region.
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*/
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void RasterizerMarkRegionCached(PAddr start, u32 size, int count_delta);
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/**
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* Flushes any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushRegion(PAddr start, u32 size);
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/**
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* Flushes and invalidates any externally cached rasterizer resources touching the given region.
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*/
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void RasterizerFlushAndInvalidateRegion(PAddr start, u32 size);
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2016-11-24 22:42:32 +03:00
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/**
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* Dynarmic has an optimization to memory accesses when the pointer to the page exists that
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* can be used by setting up the current page table as a callback. This function is used to
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* retrieve the current page table for that purpose.
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*/
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std::array<u8*, PAGE_TABLE_NUM_ENTRIES>* GetCurrentPageTablePointers();
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2015-05-13 04:38:29 +03:00
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}
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