mirror of
https://github.com/klzgrad/naiveproxy.git
synced 2024-12-01 09:46:09 +03:00
233 lines
8.8 KiB
Diff
233 lines
8.8 KiB
Diff
unchanged:
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--- protobuf-cleaned/src/google/protobuf/stubs/status.cc 2015-12-30 13:21:46.000000000 -0800
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+++ protobuf-patched/src/google/protobuf/stubs/status.cc 2016-03-31 13:25:40.888006485 -0700
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@@ -82,9 +82,9 @@
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}
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} // namespace error.
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-const Status Status::OK = Status();
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-const Status Status::CANCELLED = Status(error::CANCELLED, "");
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-const Status Status::UNKNOWN = Status(error::UNKNOWN, "");
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+const StatusPod Status::OK = { error::OK };
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+const StatusPod Status::CANCELLED = { error::CANCELLED };
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+const StatusPod Status::UNKNOWN = { error::UNKNOWN };
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Status::Status() : error_code_(error::OK) {
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}
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@@ -100,6 +100,9 @@
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: error_code_(other.error_code_), error_message_(other.error_message_) {
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}
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+Status::Status(const StatusPod& status_pod) : error_code_(status_pod.code) {
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+}
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+
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Status& Status::operator=(const Status& other) {
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error_code_ = other.error_code_;
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error_message_ = other.error_message_;
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unchanged:
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--- protobuf-cleaned/src/google/protobuf/stubs/status.h 2015-12-30 13:21:46.000000000 -0800
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+++ protobuf-patched/src/google/protobuf/stubs/status.h 2016-03-31 13:25:40.888006485 -0700
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@@ -62,6 +62,10 @@
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};
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} // namespace error
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+struct StatusPod {
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+ error::Code code;
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+};
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+
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class LIBPROTOBUF_EXPORT Status {
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public:
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// Creates a "successful" status.
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@@ -73,13 +77,14 @@
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// constructed.
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Status(error::Code error_code, StringPiece error_message);
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Status(const Status&);
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+ Status(const StatusPod&);
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Status& operator=(const Status& x);
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~Status() {}
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// Some pre-defined Status objects
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- static const Status OK; // Identical to 0-arg constructor
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- static const Status CANCELLED;
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- static const Status UNKNOWN;
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+ static const StatusPod OK;
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+ static const StatusPod CANCELLED;
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+ static const StatusPod UNKNOWN;
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// Accessor
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bool ok() const {
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only in patch2:
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unchanged:
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unchanged:
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--- protobuf-cleaned/src/google/protobuf/stubs/atomicops_internals_x86_gcc.cc
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+++ protobuf-patched/src/google/protobuf/stubs/atomicops_internals_x86_gcc.cc
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@@ -67,14 +67,12 @@ namespace internal {
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// Set the flags so that code will run correctly and conservatively, so even
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// if we haven't been initialized yet, we're probably single threaded, and our
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// default values should hopefully be pretty safe.
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-struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures = {
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+AtomicOps_x86CPUFeatureStruct AtomicOps_x86CPUFeatures_Private = {
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+ false, // uninitialized
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false, // bug can't exist before process spawns multiple threads
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false, // no SSE2
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};
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-namespace {
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-
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-// Initialize the AtomicOps_Internalx86CPUFeatures struct.
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void AtomicOps_Internalx86CPUFeaturesInit() {
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uint32_t eax;
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uint32_t ebx;
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@@ -99,6 +97,13 @@ void AtomicOps_Internalx86CPUFeaturesInit() {
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model += ((eax >> 16) & 0xf) << 4;
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}
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+ // Rarely, this function may be called from multiple threads at the same time.
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+ // To prevent races, do the initialization in a temporary struct and do a
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+ // lock-free assignment at the end. The assignment will be atomic since the
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+ // struct can fit into a single byte.
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+ AtomicOps_x86CPUFeatureStruct New_AtomicOps_x86CPUFeatures_Private;
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+ New_AtomicOps_x86CPUFeatures_Private.initialized = true;
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+
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// Opteron Rev E has a bug in which on very rare occasions a locked
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// instruction doesn't act as a read-acquire barrier if followed by a
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// non-locked read-modify-write instruction. Rev F has this bug in
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@@ -107,27 +112,17 @@ void AtomicOps_Internalx86CPUFeaturesInit() {
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if (strcmp(vendor, "AuthenticAMD") == 0 && // AMD
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family == 15 &&
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32 <= model && model <= 63) {
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- AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = true;
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+ New_AtomicOps_x86CPUFeatures_Private.has_amd_lock_mb_bug = true;
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} else {
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- AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug = false;
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+ New_AtomicOps_x86CPUFeatures_Private.has_amd_lock_mb_bug = false;
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}
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// edx bit 26 is SSE2 which we use to tell use whether we can use mfence
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- AtomicOps_Internalx86CPUFeatures.has_sse2 = ((edx >> 26) & 1);
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+ New_AtomicOps_x86CPUFeatures_Private.has_sse2 = ((edx >> 26) & 1);
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+
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+ AtomicOps_x86CPUFeatures_Private = New_AtomicOps_x86CPUFeatures_Private;
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}
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-class AtomicOpsx86Initializer {
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- public:
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- AtomicOpsx86Initializer() {
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- AtomicOps_Internalx86CPUFeaturesInit();
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- }
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-};
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-
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-// A global to get use initialized on startup via static initialization :/
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-AtomicOpsx86Initializer g_initer;
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-
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-} // namespace
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-
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} // namespace internal
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} // namespace protobuf
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} // namespace google
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unchanged:
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--- protobuf-cleaned/src/google/protobuf/stubs/atomicops_internals_x86_gcc.h
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+++ protobuf-patched/src/google/protobuf/stubs/atomicops_internals_x86_gcc.h
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@@ -33,20 +33,39 @@
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#ifndef GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_
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#define GOOGLE_PROTOBUF_ATOMICOPS_INTERNALS_X86_GCC_H_
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+#include <google/protobuf/stubs/port.h>
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+
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namespace google {
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namespace protobuf {
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namespace internal {
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-// This struct is not part of the public API of this module; clients may not
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-// use it.
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-// Features of this x86. Values may not be correct before main() is run,
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-// but are set conservatively.
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+// This struct and its associated functions are not part of the public API of
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+// this module; clients may not use it.
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+//
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+// Features of this x86.
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struct AtomicOps_x86CPUFeatureStruct {
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- bool has_amd_lock_mb_bug; // Processor has AMD memory-barrier bug; do lfence
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- // after acquire compare-and-swap.
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- bool has_sse2; // Processor has SSE2.
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+ // Whether AtomicOps_Internalx86CPUFeaturesInit was called.
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+ bool initialized : 1;
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+
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+ // Processor has AMD memory-barrier bug; do lfence after acquire
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+ // compare-and-swap.
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+ bool has_amd_lock_mb_bug : 1;
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+
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+ // Processor has SSE2.
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+ bool has_sse2 : 1;
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};
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-extern struct AtomicOps_x86CPUFeatureStruct AtomicOps_Internalx86CPUFeatures;
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+
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+// Initialize |AtomicOps_Internalx86CPUFeatures_Private|.
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+void AtomicOps_Internalx86CPUFeaturesInit();
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+
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+inline const AtomicOps_x86CPUFeatureStruct&
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+Get_AtomicOps_Internalx86CPUFeatures() {
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+ extern AtomicOps_x86CPUFeatureStruct AtomicOps_x86CPUFeatures_Private;
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+ if (GOOGLE_PREDICT_FALSE(!AtomicOps_x86CPUFeatures_Private.initialized)) {
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+ AtomicOps_Internalx86CPUFeaturesInit();
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+ }
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+ return AtomicOps_x86CPUFeatures_Private;
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+}
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#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
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@@ -89,7 +108,7 @@ inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now holds the old value of *ptr
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- if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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@@ -99,7 +118,7 @@ inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
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Atomic32 old_value,
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Atomic32 new_value) {
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Atomic32 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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- if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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@@ -131,7 +150,7 @@ inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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#else
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inline void MemoryBarrierInternal() {
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- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_sse2) {
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__asm__ __volatile__("mfence" : : : "memory");
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} else { // mfence is faster but not present on PIII
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Atomic32 x = 0;
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@@ -140,7 +159,7 @@ inline void MemoryBarrierInternal() {
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}
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inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
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- if (AtomicOps_Internalx86CPUFeatures.has_sse2) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_sse2) {
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*ptr = value;
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__asm__ __volatile__("mfence" : : : "memory");
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} else {
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@@ -213,7 +232,7 @@ inline Atomic64 Barrier_AtomicIncrement(volatile Atomic64* ptr,
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: "+r" (temp), "+m" (*ptr)
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: : "memory");
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// temp now contains the previous value of *ptr
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- if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return temp + increment;
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@@ -270,7 +289,7 @@ inline Atomic64 Acquire_CompareAndSwap(volatile Atomic64* ptr,
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Atomic64 old_value,
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Atomic64 new_value) {
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Atomic64 x = NoBarrier_CompareAndSwap(ptr, old_value, new_value);
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- if (AtomicOps_Internalx86CPUFeatures.has_amd_lock_mb_bug) {
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+ if (Get_AtomicOps_Internalx86CPUFeatures().has_amd_lock_mb_bug) {
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__asm__ __volatile__("lfence" : : : "memory");
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}
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return x;
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