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allocator: Improve MIPS coverage of spinlocks
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@ -17,12 +17,12 @@
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#define YIELD_PROCESSOR __asm__ __volatile__("pause")
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#define YIELD_PROCESSOR __asm__ __volatile__("pause")
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#elif (defined(ARCH_CPU_ARMEL) && __ARM_ARCH >= 6) || defined(ARCH_CPU_ARM64)
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#elif (defined(ARCH_CPU_ARMEL) && __ARM_ARCH >= 6) || defined(ARCH_CPU_ARM64)
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#define YIELD_PROCESSOR __asm__ __volatile__("yield")
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#define YIELD_PROCESSOR __asm__ __volatile__("yield")
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#elif defined(ARCH_CPU_MIPSEL)
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#elif defined(ARCH_CPU_MIPSEL) && __mips_isa_rev < 2
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// The MIPS32 docs state that the PAUSE instruction is a no-op on older
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// The MIPS32 docs state that the PAUSE instruction is a no-op on older
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// architectures (first added in MIPS32r2). To avoid assembler errors when
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// architectures (first added in MIPS32r2). To avoid assembler errors when
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// targeting pre-r2, we must encode the instruction manually.
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// targeting pre-r2, we must encode the instruction manually.
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#define YIELD_PROCESSOR __asm__ __volatile__(".word 0x00000140")
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#define YIELD_PROCESSOR __asm__ __volatile__(".word 0x00000140")
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#elif defined(ARCH_CPU_MIPS64EL) && __mips_isa_rev >= 2
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#elif defined(ARCH_CPU_MIPS_FAMILY) && __mips_isa_rev >= 2
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// Don't bother doing using .word here since r2 is the lowest supported mips64
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// Don't bother doing using .word here since r2 is the lowest supported mips64
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// that Chromium supports.
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// that Chromium supports.
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#define YIELD_PROCESSOR __asm__ __volatile__("pause")
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#define YIELD_PROCESSOR __asm__ __volatile__("pause")
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