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https://github.com/klzgrad/naiveproxy.git
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232 lines
6.3 KiB
ArmAsm
232 lines
6.3 KiB
ArmAsm
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#include <openssl/arm_arch.h>
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.text
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.globl _gcm_init_v8
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.private_extern _gcm_init_v8
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.align 4
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_gcm_init_v8:
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ld1 {v17.2d},[x1] //load input H
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movi v19.16b,#0xe1
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shl v19.2d,v19.2d,#57 //0xc2.0
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ext v3.16b,v17.16b,v17.16b,#8
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ushr v18.2d,v19.2d,#63
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dup v17.4s,v17.s[1]
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ext v16.16b,v18.16b,v19.16b,#8 //t0=0xc2....01
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ushr v18.2d,v3.2d,#63
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sshr v17.4s,v17.4s,#31 //broadcast carry bit
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and v18.16b,v18.16b,v16.16b
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shl v3.2d,v3.2d,#1
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ext v18.16b,v18.16b,v18.16b,#8
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and v16.16b,v16.16b,v17.16b
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orr v3.16b,v3.16b,v18.16b //H<<<=1
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eor v20.16b,v3.16b,v16.16b //twisted H
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st1 {v20.2d},[x0],#16 //store Htable[0]
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//calculate H^2
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ext v16.16b,v20.16b,v20.16b,#8 //Karatsuba pre-processing
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pmull v0.1q,v20.1d,v20.1d
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eor v16.16b,v16.16b,v20.16b
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pmull2 v2.1q,v20.2d,v20.2d
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pmull v1.1q,v16.1d,v16.1d
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ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
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eor v18.16b,v0.16b,v2.16b
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eor v1.16b,v1.16b,v17.16b
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eor v1.16b,v1.16b,v18.16b
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pmull v18.1q,v0.1d,v19.1d //1st phase
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ins v2.d[0],v1.d[1]
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ins v1.d[1],v0.d[0]
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eor v0.16b,v1.16b,v18.16b
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ext v18.16b,v0.16b,v0.16b,#8 //2nd phase
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pmull v0.1q,v0.1d,v19.1d
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eor v18.16b,v18.16b,v2.16b
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eor v22.16b,v0.16b,v18.16b
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ext v17.16b,v22.16b,v22.16b,#8 //Karatsuba pre-processing
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eor v17.16b,v17.16b,v22.16b
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ext v21.16b,v16.16b,v17.16b,#8 //pack Karatsuba pre-processed
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st1 {v21.2d,v22.2d},[x0] //store Htable[1..2]
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ret
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.globl _gcm_gmult_v8
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.private_extern _gcm_gmult_v8
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.align 4
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_gcm_gmult_v8:
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ld1 {v17.2d},[x0] //load Xi
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movi v19.16b,#0xe1
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ld1 {v20.2d,v21.2d},[x1] //load twisted H, ...
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shl v19.2d,v19.2d,#57
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#ifndef __ARMEB__
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rev64 v17.16b,v17.16b
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#endif
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ext v3.16b,v17.16b,v17.16b,#8
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pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
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eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
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pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
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pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
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ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
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eor v18.16b,v0.16b,v2.16b
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eor v1.16b,v1.16b,v17.16b
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eor v1.16b,v1.16b,v18.16b
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pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
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ins v2.d[0],v1.d[1]
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ins v1.d[1],v0.d[0]
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eor v0.16b,v1.16b,v18.16b
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ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
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pmull v0.1q,v0.1d,v19.1d
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eor v18.16b,v18.16b,v2.16b
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eor v0.16b,v0.16b,v18.16b
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#ifndef __ARMEB__
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rev64 v0.16b,v0.16b
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#endif
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ext v0.16b,v0.16b,v0.16b,#8
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st1 {v0.2d},[x0] //write out Xi
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ret
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.globl _gcm_ghash_v8
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.private_extern _gcm_ghash_v8
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.align 4
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_gcm_ghash_v8:
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ld1 {v0.2d},[x0] //load [rotated] Xi
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//"[rotated]" means that
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//loaded value would have
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//to be rotated in order to
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//make it appear as in
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//algorithm specification
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subs x3,x3,#32 //see if x3 is 32 or larger
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mov x12,#16 //x12 is used as post-
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//increment for input pointer;
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//as loop is modulo-scheduled
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//x12 is zeroed just in time
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//to preclude overstepping
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//inp[len], which means that
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//last block[s] are actually
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//loaded twice, but last
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//copy is not processed
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ld1 {v20.2d,v21.2d},[x1],#32 //load twisted H, ..., H^2
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movi v19.16b,#0xe1
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ld1 {v22.2d},[x1]
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csel x12,xzr,x12,eq //is it time to zero x12?
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ext v0.16b,v0.16b,v0.16b,#8 //rotate Xi
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ld1 {v16.2d},[x2],#16 //load [rotated] I[0]
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shl v19.2d,v19.2d,#57 //compose 0xc2.0 constant
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#ifndef __ARMEB__
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rev64 v16.16b,v16.16b
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rev64 v0.16b,v0.16b
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#endif
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ext v3.16b,v16.16b,v16.16b,#8 //rotate I[0]
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b.lo Lodd_tail_v8 //x3 was less than 32
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ld1 {v17.2d},[x2],x12 //load [rotated] I[1]
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#ifndef __ARMEB__
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rev64 v17.16b,v17.16b
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#endif
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ext v7.16b,v17.16b,v17.16b,#8
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eor v3.16b,v3.16b,v0.16b //I[i]^=Xi
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pmull v4.1q,v20.1d,v7.1d //H·Ii+1
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eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
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pmull2 v6.1q,v20.2d,v7.2d
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b Loop_mod2x_v8
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.align 4
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Loop_mod2x_v8:
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ext v18.16b,v3.16b,v3.16b,#8
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subs x3,x3,#32 //is there more data?
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pmull v0.1q,v22.1d,v3.1d //H^2.lo·Xi.lo
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csel x12,xzr,x12,lo //is it time to zero x12?
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pmull v5.1q,v21.1d,v17.1d
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eor v18.16b,v18.16b,v3.16b //Karatsuba pre-processing
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pmull2 v2.1q,v22.2d,v3.2d //H^2.hi·Xi.hi
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eor v0.16b,v0.16b,v4.16b //accumulate
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pmull2 v1.1q,v21.2d,v18.2d //(H^2.lo+H^2.hi)·(Xi.lo+Xi.hi)
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ld1 {v16.2d},[x2],x12 //load [rotated] I[i+2]
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eor v2.16b,v2.16b,v6.16b
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csel x12,xzr,x12,eq //is it time to zero x12?
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eor v1.16b,v1.16b,v5.16b
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ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
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eor v18.16b,v0.16b,v2.16b
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eor v1.16b,v1.16b,v17.16b
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ld1 {v17.2d},[x2],x12 //load [rotated] I[i+3]
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#ifndef __ARMEB__
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rev64 v16.16b,v16.16b
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#endif
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eor v1.16b,v1.16b,v18.16b
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pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
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#ifndef __ARMEB__
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rev64 v17.16b,v17.16b
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#endif
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ins v2.d[0],v1.d[1]
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ins v1.d[1],v0.d[0]
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ext v7.16b,v17.16b,v17.16b,#8
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ext v3.16b,v16.16b,v16.16b,#8
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eor v0.16b,v1.16b,v18.16b
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pmull v4.1q,v20.1d,v7.1d //H·Ii+1
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eor v3.16b,v3.16b,v2.16b //accumulate v3.16b early
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ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
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pmull v0.1q,v0.1d,v19.1d
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eor v3.16b,v3.16b,v18.16b
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eor v17.16b,v17.16b,v7.16b //Karatsuba pre-processing
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eor v3.16b,v3.16b,v0.16b
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pmull2 v6.1q,v20.2d,v7.2d
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b.hs Loop_mod2x_v8 //there was at least 32 more bytes
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eor v2.16b,v2.16b,v18.16b
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ext v3.16b,v16.16b,v16.16b,#8 //re-construct v3.16b
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adds x3,x3,#32 //re-construct x3
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eor v0.16b,v0.16b,v2.16b //re-construct v0.16b
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b.eq Ldone_v8 //is x3 zero?
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Lodd_tail_v8:
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ext v18.16b,v0.16b,v0.16b,#8
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eor v3.16b,v3.16b,v0.16b //inp^=Xi
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eor v17.16b,v16.16b,v18.16b //v17.16b is rotated inp^Xi
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pmull v0.1q,v20.1d,v3.1d //H.lo·Xi.lo
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eor v17.16b,v17.16b,v3.16b //Karatsuba pre-processing
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pmull2 v2.1q,v20.2d,v3.2d //H.hi·Xi.hi
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pmull v1.1q,v21.1d,v17.1d //(H.lo+H.hi)·(Xi.lo+Xi.hi)
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ext v17.16b,v0.16b,v2.16b,#8 //Karatsuba post-processing
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eor v18.16b,v0.16b,v2.16b
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eor v1.16b,v1.16b,v17.16b
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eor v1.16b,v1.16b,v18.16b
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pmull v18.1q,v0.1d,v19.1d //1st phase of reduction
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ins v2.d[0],v1.d[1]
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ins v1.d[1],v0.d[0]
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eor v0.16b,v1.16b,v18.16b
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ext v18.16b,v0.16b,v0.16b,#8 //2nd phase of reduction
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pmull v0.1q,v0.1d,v19.1d
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eor v18.16b,v18.16b,v2.16b
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eor v0.16b,v0.16b,v18.16b
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Ldone_v8:
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#ifndef __ARMEB__
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rev64 v0.16b,v0.16b
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#endif
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ext v0.16b,v0.16b,v0.16b,#8
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st1 {v0.2d},[x0] //write out Xi
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ret
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.byte 71,72,65,83,72,32,102,111,114,32,65,82,77,118,56,44,32,67,82,89,80,84,79,71,65,77,83,32,98,121,32,60,97,112,112,114,111,64,111,112,101,110,115,115,108,46,111,114,103,62,0
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.align 2
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.align 2
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